Abstract: A novel networking architecture and technique for reducing system latency caused, at least in part, by access contention for usage of common bus and memory facilities, wherein a separate data processing and queue management forwarding engine and queue manager are provided for each I/O module to process packet/cell control information and delivers queuing along a separate path that eliminates contention with other resources and is separate from the transfer of packet/cell data into and from the memory.
Type:
Grant
Filed:
July 25, 1997
Date of Patent:
June 29, 1999
Assignee:
NeoNet LLC
Inventors:
Tim Wright, Peter Marconi, Richard Conlin, Zbigniew Opalka