Abstract: A method of crystallizing an amorphous semiconductor thin film formed on a substrate is provided. The method includes the steps of: forming a gate insulation film and a gate electrode on an amorphous semiconductor thin film; locally forming first and second crystallization induced metal patterns for inducing crystallization of the amorphous semiconductor thin film, on part of the amorphous semiconductor thin film spaced at a predetermined off-set distance from the gate insulation film; ion-injecting impurities into the substrate to thus define a source/drain region; forming a protection film on the whole surface of the substrate; and heat-treating the substrate in the air to thereby crystallize the amorphous semiconductor thin film.

Abstract: A low-temperature poly-crystalline thin film transistor in which amorphous silicon is crystallized using a laser crystallization method or a metal induced lateral crystallization method shows an unstable electrical property since crystallization is accomplished at a low temperature. When an electrical stress is applied to the low-temperature poly-crystalline thin film transistor and a lower substrate for a display device including the same, an electrical feature thereof is enhanced. To apply an electrical stress to the low-temperature poly-crystalline thin film transistor, the source of a thin film transistor is grounded, and a critical voltage which is determined according to a gate voltage applied between the drain and the source of the thin film transistor, at a state where any gate voltage has been applied between the gate and the source of the thin film transistor.

Abstract: A method of forming wires of a poly-crystalline TFT by crystallizing an amorphous silicon thin film using a metal film is provided. The wires forming method includes the steps of: removing a MILC metal film; forming etch-stopper layer patterns on at least part of respective source and drain regions formed on a semiconductor layer; forming an interlayer insulation film on the substrate; etching the interlayer insulation film to thereby form contact holes which expose the etch-stopper layer patterns of the source and drain regions; and forming a wires metal film contacting the etch-stopper layer patterns, and patterning the wires metal film to thus form metal wires. Thus, as the etch-stopper layer patterns are additionally installed at the contact positions, a silicon thin film can be protected at etching the interlayer insulation film.

Abstract: A poly-silicon (poly-Si) thin film transistor (TFT) having a back bias effect is provided in order to enhance characteristics of a leakage current, a sub-threshold slope, and an on-current. The poly-Si TFT includes a glass substrate, an island type buried electrode pad formed of an conductive material on one side of the glass substrate where the back bias voltage is applied, a buffer layer formed of an insulation material on the whole surface of the glass substrate, and a poly-Si TFT formed on the upper portion of the buffer layer. A method of fabricating the TFT is also provided.