Abstract: A method of battery capacity measurement is actualized by battery internal resistance. This method establishes a controlled discharge path inside the battery module. The battery discharge current is a constant value despite of the variation of system loading current. The internal resistance measured by establishing this constant battery current can be used to obtain the battery capacity precisely.

Abstract: A lithium battery module with multiple-cells connected in parallel is disclosed. The lithium battery module comprises a battery management unit, a power converter (optional) and each cell with an individual charging control switch and a discharging control switch in series connected with the cell and is independent controlled by the battery management unit so that a charger is capable of charging the designate cell or more or disable one among them.

Abstract: A device for predicting remaining capacity of a battery and a method for the same are disclosed. The device is embedded in a battery pack or externally coupled thereto. The device includes a program for proceeding an algorithm of cell capacity calculation, a database stored in a non-volatile memory having a table of open-circuit voltage, a table of current gain and a capacity conversion equation. The program generates a discharging curve according to the cell temperature and load accessed and corrects the database according to the battery voltage and the discharging curve and the coulomb counter.

Abstract: A battery pack detection circuit that can detect cold or false welding, charging status, and discharging status is disclosed. The battery pack detection circuit comprises a driving circuit electrically connected to a switch unit outside the battery pack detection circuit; a voltage detection and comparison circuit electrically connected to a multi-cell battery pack having a plurality of battery cells outside the battery pack detection circuit, wherein the voltage detection and comparison circuit is configured to detect cell voltages across each of the battery cells under at least two circuit connection conditions and compare the differences in cell voltage with a predetermined value, wherein the differences in cell voltage are derived from a subtraction operation performed on the cell voltages measured under the at least two circuit connection conditions; and an interface and control unit configured to receive commands from a SMBUS and provide a signal to a detection load.

Abstract: The battery module comprises a main battery, a voltage converter, an auxiliary device, a battery management unit and a first set of switching devices and a second set of switching devices. The main battery provides the electric power. The auxiliary device is used to store the electric power. The battery management unit controls the main battery and the auxiliary device to charge or discharge through a first set of switching devices and a second set of switching devices, respectively. When the battery module is charged by an external charger, the auxiliary device and the main battery are charged simultaneously. When the external charger stops to charge the battery module, the battery management unit controls the auxiliary device through the second set of switching devices to continuously charge the main battery through the voltage converter.

Abstract: A lithium battery module with multiple-cells connected in parallel is disclosed. The lithium battery module comprises a battery management unit, a power converter (optional) and each cell with an individual charging control switch and a discharging control switch in series connected with the cell and is independent controlled by the battery management unit so that a charger is capable of charging the designate cell or more or disable one among them.

Abstract: A method of battery capacity measurement is actualized by battery internal resistance. This method establishes a controlled discharge path inside the battery module. The battery discharge current is a constant value despite of the variation of system loading current. The internal resistance measured by establishing this constant battery current can be used to obtain the battery capacity precisely.

Abstract: A battery protector with internal impedance compensation comprises: a logic circuit and delay module, an overcharge comparator, and an over-discharge comparator. The overcharge comparator has a positive terminal connected with a first adjustable reference signal and the over-discharge comparator has a negative terminal connected with a second adjustable reference signal and both of the other terminals of comparator are fed by the same partial voltage of the same voltage divider, which has two terminals, respectively, connected with the two electrodes of the battery. The first adjustable reference signal and the second adjustable reference are varied with the charging current or discharging current and the internal impedance of the battery.

Abstract: A battery management system includes an external non-volatile memory and a battery management chip with embedded SRAM, CPU, ROM, and ROM_RAM encoder. The chip communicates with the non-volatile memory via standard protocols. While the battery management system is powered on or reset, a battery management program stored in the non-volatile memory is loaded to the embedded SRAM and the executed by CPU. As turning off this system, the program in the SRAM is then restored back the non-volatile memory. A battery protection IC is optionally embedded in the chip or externally connected with this chip to protect the battery from over-/under-voltage, over-current and short-circuit in both charge and discharge.

Abstract: A battery management system for measuring remaining charges in a battery packet with multi-cells is disclosed. The battery comprises electric property and non-electric property measuring modules, multi-cells, a slave communication protocol controller, and a battery protective circuit. The portable device comprises an embedded controller and a charge gauge module and a master communication protocol controller. The parameters demanded for calculating the remaining charges of the multi-cells are measured by the electric property and non-electric property measurement modules and transferred through the SMBus interface to the embedded controller and the charge gauge module. Therefore, the battery management system can manage the remaining charges of every cell in the multi-cells without a microprocessor in the battery packet.

Abstract: A battery protection IC using charging control pin, Cout, so as to reduce delay time during CP test or FT test for is disclosed. The battery protection IC has a delay time control circuit including a comparator and a delay signal selector. The comparator has a negative input terminal connected to VCC, a positive input terminal connected with the Cout pin and an output terminal connected to the delay signal selector. To perform foregoing test, a voltage source is added to activate the short delay time mode rather than a normal delay time one.

Abstract: A binary bidirectional trimming circuit is disclosed. The trimming circuit includes: a first resistor set having 4 resistors in parallel connected and a first fuse bridged two ends thereto provide one trimming step; a second resistor set having 2 resistors in series connected and a second fuse bridged two ends thereto provide eight trimming steps; a third resistor set having 2 resistors in parallel connected and a third fuse bridged two ends thereto provide two trimming steps; a fourth resistor set having 1 resistor and a fourth fuse bridged two ends thereto provide four trimming steps; a first loading resistor; and a second loading resistor. The first resistor set, second resistor set, first loading resistor, third resistor set, the fourth resistor set, and the second loading resistor are in series connected.

Abstract: A time delay circuit in a battery protection chip for an internal time delay or external time delay selection is disclosed. The protection chip has a selective pin for choosing the internal time delay while the selective pin is floated or the external time delay while the selective pin is connected with a capacitor. The time delay circuit is composed of a charge-discharge circuit, a D flip-flop, a RS latch, a NOR gate, and a 2 to 1 multiplexer (MUX 2:1). According to an embodiment, if the selective pin is floated, the outputs of the D flip-flop, and the RS latch will make MUX 2:1 choose an output signal of the NOR gate having input signals of an internal delay signal and input signal. On the other hand, if the selective pin is connected with an external capacitor having an external capacitance of more than 250 pF, the output signal of the D flip-flop, and the RS latch will make MUX 2:1 choose an output of the charge-discharge circuit but ignore the internal delay signal.

Abstract: A wake-up circuit includes a counter, a register circuit, a first logic circuit, an oscillator, a flip flop, and a second logic circuit. The wake-up circuit receives a standby signal to stop the oscillator working and to wait for the wake-up signal to reactivate the oscillator again. When the duration of the wake-up signal is shorter than an expected time of the counter, the oscillator stops working again and re-enters the saving mode. When the duration of the wake-up signal is longer than the expected time of the counter, the counter controls the flip flop to output a preset signal to the register circuit, and as a result that keeps the oscillator working even after the wake-up signal is removed by the first logic circuit operating, and then the second logic circuit operates with flip-flop to set the counter returning to a normal state to wait for a next standby signal to feed in.

Abstract: A battery management system includes a flash memory chip having a smart battery management program and a microprocessor. An interface model (I/F module) is installed in the microprocessor as a bridge between the flash chip and the microprocessor. The I/F module includes a data register and an address register as a data buffer and address buffer, respectively, between the CPU and the flash chip. The I/F module also includes a logic control circuit to generate signals for the flash chip to read and program.