Patents Assigned to Nepes Co., Ltd.
  • Publication number: 20210398869
    Abstract: A semiconductor package includes an upper structure including a semiconductor chip and a first molding layer for molding the semiconductor chip, a lower structure provided on the upper structure, the lower structure including a conductive post and a second molding layer for molding the conductive post, and a redistribution structure provided between the upper structure and the lower structure, the redistribution structure including a wiring pattern for electrically connecting a pad of the semiconductor chip to the conductive post, in which a thermal expansion coefficient of the second molding layer is different from a thermal expansion coefficient of the first molding layer.
    Type: Application
    Filed: October 17, 2019
    Publication date: December 23, 2021
    Applicant: NEPES CO., LTD.
    Inventors: Su Yun KIM, Dong Hoon OH, Yong Tae KWON, Jun Kyu LEE, Kyeong Rok SHIN, Yong Woon YEO
  • Publication number: 20210343656
    Abstract: A semiconductor package includes a semiconductor chip including a chip pad, a first insulating layer provided on the semiconductor chip and including a first via hole, a first wiring pattern provided on the first insulating layer and connected to the chip pad through the first via hole of the first insulating layer, a second insulating layer provided on the first insulating layer and the first wiring pattern and including a second via hole, and a second wiring pattern provided on the second insulating layer and connected to the first wiring pattern through the second via hole of the second insulating layer, wherein the first insulating layer includes a first upper surface in contact with the second insulating layer and a first lower surface opposite to the first upper surface, and the first upper surface of the first insulating layer has surface roughness greater that the first lower surface of the first insulating layer.
    Type: Application
    Filed: September 26, 2019
    Publication date: November 4, 2021
    Applicant: Nepes Co., Ltd.
    Inventors: Yong Tae KWON, Jun Kyu Lee, Dong Hoon OH, Su Yun KIM, Kyeong Rok SHIN
  • Publication number: 20210313274
    Abstract: A semiconductor package is provided. The semiconductor package can include a first redistributed layer on which a plurality of semiconductor chips and a plurality of passive devices are mounted on one surface, a second redistributed layer electrically connected to the first redistributed layer through a via, an external connection terminal formed on the lower surface of the second redistributed layer, a first mold provided to cover the plurality of semiconductor chips and the plurality of passive devices on the first redistributed layer, and a second mold provided between the first redistributed layer and the second redistributed layer. Each of the first redistributed layer and the second redistributed layer includes a wiring pattern and an insulating layer and is composed of a plurality of layers, and at least one of the plurality of semiconductor chips is disposed between the first redistributed layer and the second redistributed layer.
    Type: Application
    Filed: April 1, 2021
    Publication date: October 7, 2021
    Applicant: NEPES CO., LTD.
    Inventors: Sang Yong PARK, Juhyun NAM
  • Publication number: 20210288005
    Abstract: A semiconductor package includes a semiconductor chip having at least one chip pad disposed on one surface thereof; a wiring pattern disposed on top of the semiconductor chip and having at least a portion thereof in contact with the chip pad to be electrically connected to the chip pad; and a solder bump disposed on outer surface of the wiring pattern to be electrically connected to the chip pad through the wiring pattern.
    Type: Application
    Filed: February 19, 2021
    Publication date: September 16, 2021
    Applicant: Nepes CO., LTD.
    Inventors: Hyun Sik KIM, Seung Hwan SHIN, Yong Tae KWON, Dong Hoon SEO, Hee Cheol KIM, Dong Soo LEE
  • Publication number: 20210193602
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a lower structure including a semiconductor chip having a chip terminal; an external connection terminal connecting the semiconductor chip to an external device, and an intermediate connection structure including an upper surface and a lower surface opposite to the upper surface, and positioned between the lower structure and the external connection terminal.
    Type: Application
    Filed: December 15, 2020
    Publication date: June 24, 2021
    Applicant: Nepes CO., LTD.
    Inventors: Jun Kyu LEE, Su Yun Kim, Dong Hoon OH, Yong Tae KWON, Ju Hyun NAM
  • Patent number: 11011502
    Abstract: A semiconductor package includes a first package including a first semiconductor chip, a first encapsulation layer that covers the first semiconductor chip, and a first redistribution pattern connected to pads of the first semiconductor chip and a second package on the first package, the second package including a second semiconductor chip, a second encapsulation layer that covers the second semiconductor chip, and a second redistribution pattern connected to pads of the second semiconductor chip. The first redistribution pattern is connected to the second redistribution pattern through the first encapsulation layer.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: May 18, 2021
    Assignee: Nepes Co., Ltd.
    Inventor: Jun Kyu Lee
  • Patent number: 10964656
    Abstract: The present invention relates to a semiconductor package and a method of manufacturing the same. In a semiconductor package which electrically connects a semiconductor chip and a printed circuit board using a solder ball, the semiconductor package further includes a thermal buffer layer which is positioned on a semiconductor chip, absorbs and disperse heat generated by the semiconductor chip, increases a distance between the semiconductor chip and a printed circuit board to decrease a deviation of a heat conduction process, and has a thickness ranging from 7.5 to 50% of a diameter of a solder ball.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: March 30, 2021
    Assignee: NEPES CO., LTD.
    Inventors: Yong Tae Kwon, Hee Cheol Kim, Seung Jun Moon, Jini Shim
  • Publication number: 20210091008
    Abstract: A semiconductor package having improved impact resistance and excellent heat dissipation and electromagnetic wave shielding property, and a manufacturing method thereof are provided. There is provided a semiconductor package including: a chip having a contact pad provided on one surface thereof; a buffer layer formed on one surface of the chip; one or more wiring patterns disposed on the buffer layer, electrically connected to the contact pad of the chip, and extended to an outside of the chip; an external pad provided on the wiring pattern and electrically connected to the wiring pattern; an external connection terminal electrically connected to the external pad; and a mold layer formed to surround the other surface and a side surface of the chip and a side surface of the buffer layer, and formed up to the other surface of the wiring pattern.
    Type: Application
    Filed: September 21, 2020
    Publication date: March 25, 2021
    Applicant: Nepes CO., LTD.
    Inventors: Dong Hoon Oh, Su Yun Kim, Ju Hyun Nam
  • Patent number: 10957654
    Abstract: Provided are a semiconductor package and a method of manufacturing the same, the semiconductor package including an interconnection part including an insulation layer and an interconnection layer, a semiconductor chip disposed on the interconnection part and electrically connected to the interconnection layer through a bonding pad, and an EMI shielding part connected to the interconnection layer while covering the semiconductor chip and the interconnection part.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: March 23, 2021
    Assignee: NEPES CO., LTD.
    Inventors: Jun-Kyu Lee, Jaecheon Lee
  • Publication number: 20210066154
    Abstract: A semiconductor package according to an exemplary embodiment of the present disclosure may comprise a semiconductor chip comprising a chip pad; a redistribution layer electrically connected to the chip pad of the semiconductor chip; an external connection terminal electrically connected to the redistribution layer; a sealing material covering the semiconductor chip and configured to fix the semiconductor chip and the redistribution layer; an adhesive film positioned on the upper surface of the sealing material; and a heat sink formed on the upper surface of the adhesive film and having a stepped portion at the periphery thereof.
    Type: Application
    Filed: November 13, 2020
    Publication date: March 4, 2021
    Applicant: NEPES CO., LTD.
    Inventors: Nam Chul Kim, Jong Heon Kim, Eung Ju Lee, Yong Woon Yeo, Chang Woo Lee
  • Publication number: 20200273830
    Abstract: A semiconductor package according to an embodiment includes a semiconductor chip having a first surface in which a chip pad is formed, a first insulating layer arranged on the first surface of the semiconductor chip and including a first filler, a first conductive via electrically connected to the chip pad and formed to penetrate the first insulating layer, a redistribution pattern electrically connected to the first conductive via and buried in the first insulating layer, a second insulating layer contacting the redistribution pattern on the first insulating layer and including a second filler, a second conductive via electrically connected to the redistribution pattern and formed to penetrate the second insulating layer, an under bump material (UBM) electrically connected to the second conductive via and buried in the second insulating layer, and an external connection terminal electrically connected to the UBM.
    Type: Application
    Filed: February 17, 2020
    Publication date: August 27, 2020
    Applicant: Nepes Co., Ltd.
    Inventors: Yong Tae Kwon, Jun Kyu LEE, Kyeong Rok SHIN
  • Publication number: 20200203265
    Abstract: A semiconductor package includes a semiconductor chip including a chip pad on a first surface thereof, an external pad electrically connected to the chip pad of the semiconductor chip, an external connection terminal covering the external pad, and an intermediate layer between the external pad and the external connection terminal, the intermediate layer including a third metal material that is different from a first metal material included in the external pad and a second metal material included in the external connection terminal.
    Type: Application
    Filed: December 23, 2019
    Publication date: June 25, 2020
    Applicant: NEPES CO., LTD.
    Inventors: Gi Jo JUNG, Chang Yong JO, Young Mo LEE, Jung Sic OH, Jong Ho HAN
  • Publication number: 20190333809
    Abstract: A technical concept of the present disclosure provides a method of producing a semiconductor package, the method including operations of: arranging a plurality of wafers on a tray, forming an interconnect structure on the tray and the plurality of wafers, and separating the plurality of wafers from the tray.
    Type: Application
    Filed: July 9, 2019
    Publication date: October 31, 2019
    Applicant: NEPES CO., LTD.
    Inventors: Nam Chul Kim, Yong Woon Yeo, Yong Tae Kwon, Young Seok Lee
  • Patent number: 10410968
    Abstract: Disclosed are a semiconductor package including a through via and a method of manufacturing the same. The semiconductor package includes a frame having an accommodation part and configured to transmit an electrical signal between upper and lower portions thereof through a through via provided around the accommodation part, one or more semiconductor chips accommodated in the accommodation part, a wiring part provided below the frame and the semiconductor chips and configured to connect the through via to the semiconductor chips, an encapsulant molded to integrate the frame and the semiconductor chips, and a conductive ball or a conductive post connected to an upper portion of the through via.
    Type: Grant
    Filed: November 16, 2016
    Date of Patent: September 10, 2019
    Assignee: NEPES CO., LTD.
    Inventor: Yunmook Park
  • Patent number: 10381312
    Abstract: Disclosed herein are a semiconductor package and a method of manufacturing the same. The semiconductor package according to embodiments of the present disclosure includes a wiring including a plurality of layers including an insulating layer and a wiring layer, a semiconductor chip mounted on the wiring and electrically connected to the wiring layer through a bonding pad, a cover member configured to cover side surfaces of the semiconductor chip and the wiring and be in contact with at least one wiring layer, and an encapsulant configured to seal the cover member. Accordingly, the cover member covers the semiconductor chip and is in contact with the wiring formed under the semiconductor chip, thereby reducing electromagnetic interference, minimizing noise between operations of the semiconductor package, and improving a signal speed.
    Type: Grant
    Filed: May 11, 2017
    Date of Patent: August 13, 2019
    Assignee: NEPES CO., LTD.
    Inventors: Il-Hwan Kim, Jun-Kyu Lee, Min-A Yoon, Dong-Hoon Oh, Tae-Won Kim
  • Publication number: 20190237407
    Abstract: Provided are a semiconductor package and a method of manufacturing the same, the semiconductor package including an interconnection part including an insulation layer and an interconnection layer, a semiconductor chip disposed on the interconnection part and electrically connected to the interconnection layer through a bonding pad, and an EMI shielding part connected to the interconnection layer while covering the semiconductor chip and the interconnection part.
    Type: Application
    Filed: January 18, 2019
    Publication date: August 1, 2019
    Applicant: NEPES CO., LTD.
    Inventors: Jun-Kyu LEE, Jaecheon Lee
  • Publication number: 20190229101
    Abstract: A semiconductor package includes a first package including a first semiconductor chip, a first encapsulation layer that covers the first semiconductor chip, and a first redistribution pattern connected to pads of the first semiconductor chip and a second package on the first package, the second package including a second semiconductor chip, a second encapsulation layer that covers the second semiconductor chip, and a second redistribution pattern connected to pads of the second semiconductor chip. The first redistribution pattern is connected to the second redistribution pattern through the first encapsulation layer.
    Type: Application
    Filed: January 8, 2019
    Publication date: July 25, 2019
    Applicant: NEPES CO., LTD.
    Inventor: Jun Kyu Lee
  • Publication number: 20190122899
    Abstract: A semiconductor package comprising a fan-out structure and a manufacturing method therefor are disclosed. A semiconductor package according to an embodiment of the present invention comprises: a wiring unit comprising an insulation layer and a wiring layer; a semiconductor chip mounted on the wiring unit and coupled to the wiring layer by flip-chip bonding; a filling member for filling a gap between the semiconductor chip and the wiring unit; and a film member for performing coating so as to cover one surface of each of the semiconductor chip, the filling member, and the wiring unit.
    Type: Application
    Filed: April 3, 2017
    Publication date: April 25, 2019
    Applicant: NEPES CO., LTD.
    Inventors: Yong-Tae KWON, Jun-Kyu LEE, Si Woo LIM, Dong Hoon OH, Jun Sung MA, Tae-Won KIM
  • Patent number: 9793251
    Abstract: Disclosed herein is a semiconductor package in which a semiconductor chip and a mounting device are packaged together. The semiconductor package includes a semiconductor chip, a mounting block on which a first mounting device is mounted on a substrate that includes a circuit formed thereon, and an interconnection part configured to electrically connect the semiconductor chip to the mounting block.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: October 17, 2017
    Assignee: NEPES CO., LTD.
    Inventors: Jun-Kyu Lee, Yong-Tae Kwon
  • Patent number: 9754892
    Abstract: Disclosed herein is a stacked semiconductor package in which semiconductor chips having various sizes are stacked. In accordance with one aspect of the present disclosure, a stacked semiconductor package includes a first semiconductor chip structure provided with a first semiconductor chip, a first mold layer surrounding the first semiconductor chip, and a first penetration electrode passing through the first mold layer and electrically connected to the first semiconductor chip, and a second semiconductor chip structure vertically stacked on the first semiconductor chip structure and provided with a second semiconductor chip and a second penetration electrode electrically connected to the first penetration electrode, wherein the first semiconductor chip structure may have the same size as the second semiconductor chip structure.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: September 5, 2017
    Assignee: NEPES CO., LTD.
    Inventors: Yong-Tae Kwon, Jun-Kyu Lee