Abstract: A semiconductor chip having a solder bump and a method of fabricating the same are provided. Conventionally, an inter-metallic compound (IMC) unexpectedly grows at an interface of the solder bump by means of heat generated during operation of the semiconductor chip, thereby weakening mechanical property of the semiconductor chip. To solve this drawback, the semiconductor chip includes at least one metal adhesion layer formed on an electrode pad of the semiconductor chip, an interlayer isolation layer formed on the metal adhesion layer, at least one penetration layer formed on the interlayer isolation layer and penetrating into the solder bump, and the solder bump formed on the penetration layer. Thereby, materials of the penetration layer penetrate into the solder bump to change the solder bump into a multi-component solder bump, so that the growth of the IMC is suppressed, and the reliability of the semiconductor chip can be improved.

Abstract: There is provided an ultra slim semiconductor package comprising: a multilayer thin film layer including at least one or more dielectric layers and at least one or more redistribution layers; at least one semiconductor chip electrically connected to the redistribution layer and mounted on the multilayer thin film layer; conductive structures electrically connected to the redistribution layer and each formed in a post shape at one side of the multilayer thin film layer; a molding part formed on the multilayer thin film layer and at least partially covering the conductive structures and the semiconductor chip; and bumps for external connection formed on the molding part and electrically connected to the conductive structures. The semiconductor package according to the present invention enables mass production at wafer level, is easily stacked between the packages, and has an excellent electrical characteristic.

Abstract: There is provided a system-in-package (SiP), which includes a substrate obtained by cutting a wafer for each unit system; one or more first electronic devices mounted on the substrate by a heat radiation plate; a plurality of interlayer dielectrics sequentially formed on the substrate; and one or more second electronic devices buried between or in the interlayer dielectrics on the substrate. A heat sink may be additionally attached to the bottom surface of the substrate. In this case, a thermal conduction path including heat pipes connecting the heat radiation plate on the substrate and the heat sink is formed. In the SiP, various types of devices are buried at a wafer level, so that a more integrated semiconductor device is implemented corresponding to demand for a fine pitch. Further, the heat radiation of a device required in high-speed operation and high heat generation is maximized due to the multi-stepped heat radiation structure, and thus the operation of the device is more stabilized.

Abstract: There is provided a semiconductor package comprising: a multilayer thin film structure including a plurality of dielectric layers and at least one or more redistribution layers; a semiconductor chip positioned at one side of the multilayer thin film structure and electrically connected to the redistribution layer; and a solder bump formed at the other side of the multilayer thin film structure. The multilayer thin film structure functions as the substrate for the semiconductor package and realizes the light, thin, short and small BGA package without any additional substrate. A plurality of the packages can be simultaneously formed at wafer level or carrier level, to simplify the process and to be favorable for mass production.