Abstract: A method of mapping logical block select signals to physical blocks can include receiving at least one signal for each of n+1 logical blocks, where n is an integer greater than one, that each map to one of m+1 physical blocks, where n<m. The method also includes mapping the at least one signal for each logical block to physical block from a corresponding a set of r+1 physical blocks, each set of r+1 physical blocks being different from one another.

Abstract: A multiple match circuit generates a multiple match flag for an associated CAM array having n words by logically ORing k=log2n intermediate multiple match flags. Each of the intermediate multiple match flags is generated in response to a unique logical combination of a plurality of match line signals corresponding to the n CAM words. For one embodiment, the first n/2 match line signals are logically ORed and the second n/2 match line signals are logically ORed. The resultant OR output signals are logically ANDed to generate a first intermediate multiple match flag. Then, the first n/4 match line signals and the second n/4 match line signals are each logically ORed together, and the resulting OR output signals are logically ANDed together to generate a first signal. The third n/4 match line signals and the fourth n/4 match line signals are combined in a similar manner to generate a second signal. These first and second signals are logically ORed to generate a second intermediate multiple match flag.

Abstract: A match line control circuit includes a weak, static pull-up transistor and a strong, dynamic pull-up transistor coupled between a match line of an associated CAM and a supply voltage. Prior to compare operations, both the static pull-up transistor and the dynamic pull-up transistor are in a conductive state and thereby quickly charge the match line to the supply voltage. During compare operations, the dynamic transistor is turned off to reduce current flow between the supply voltage and the match line. In some embodiments, the static pull-up transistor and the dynamic pull-up transistor are configured to match the parasitics of the CAM cells 10 coupled to the match line, thereby increasing performance of the associated CAM.

Abstract: A method and apparatus for simultaneously performing a plurality compare operations in a content addressable memory (CAM) device. For one embodiment, the CAM device includes a CAM array having a plurality of CAM cells, a first comparand register for storing first comparand data, and a second comparand register for storing second comparand data. Each CAM cell receives the first comparand data over a first set of compare lines, and receives the second comparand data over a second set of compare lines. Each CAM cell has a memory cell and multiple compare circuits that can individually and simultaneously compare the first and second comparand data with data stored in the memory cell. The result of each comparison is reflected on a corresponding match line. The match lines are then selectively coupled to a priority encoder to determine a match address corresponding to each compare operation. For one embodiment, the CAM cells may be ternary CAM cells each having a mask cell.