Abstract: An integrated circuit device for delivering power to a load includes a controller circuit, a cascade circuit, and a power delivery circuit. The controller circuit generates a plurality of control signals. The cascade circuit receives the control signals from the controller circuit and sequentially outputs the control signals onto a cascade bus. The power delivery circuit receives the control signals from the controller circuit and delivers an amount of current to the load, in response to one of the control signals.

Abstract: A content addressable memory (CAM) row is disclosed. The CAM row includes one or more compare circuits coupled between a match line and a virtual-ground line. The compare circuits are configured to compare a search key with CAM cell data words. The CAM row also includes a pre-charge circuit controlled by a pre-charge signal, and includes a tank capacitor. The pre-charge circuit is configured to pre-charge the match line to a supply voltage in response to assertion of the pre-charge signal. A pull-down transistor dynamically discharges the virtual-ground line to ground potential.

Abstract: A system and method are disclosed for securely transmitting and receiving a signal. A nonlinear keying modulator is used in the transmitter to encrypt the signal using a nonlinear keying modulation technique. A nonlinear keying demodulator is used in the receiver to decrypt the signal.

Abstract: Integrated circuit devices are disclosed with receive ports having mapping circuits automatically configurable to change a logical mapping of data received on receive-data connections. Automatic configuration can be based on a data value included within a received data set. Corresponding systems and methods are also described.

Abstract: A circuit for the analog correlation of a signal to remove impairments such as echo, cross talk and intersymbol interference is described. A duplexing circuit which improves echo response by providing a second transformer is described.

Abstract: A CAM device for comparing a search key with a plurality of ternary words stored in a CAM array includes one or more population counters, a pre-compare memory, and a pre-compare circuit. The present embodiments reduce the power consumption of CAM devices during compare operations between a search key and ternary words stored in a CAM array by selectively enabling the match lines in the CAM array in response to pre-compare operations between a set of population counts corresponding to the masked search key and a set of population counts corresponding to the ternary words stored in the CAM array.

Abstract: A receiver circuit for coupling to a serial link is disclosed. The receiver circuit comprises a data buffer and serial interface circuitry. The serial interface circuitry receives serialized packet words and processes the serial words for input to the data buffer. The serial interface circuitry includes word detection logic to detect predefined control words and discard logic to selectively inhibit forwarding of one or more of the predefined control words to the data buffer.

Abstract: A content addressable memory (CAM) device has an array including a plurality of CAM rows that are partitioned into row segments, wherein a respective row includes a first row segment including a number of first CAM cells coupled to a first match line segment, a second row segment including a number of second CAM cells coupled to a second match line segment, and a circuit to selectively pre-charge the first match line segment in response to a value indicating whether data stored in the first row segment of the respective row is the same as data stored in the first row segment of another row. Power consumption can be reduced during compare operations in which the first row segment of another row that stores the same data as the first row segment of the respective row is not enabled.

Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. The data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. In one aspect of an embodiment of the invention, the messaging network connects to a high-bandwidth star-topology serial bus such as a PCI express (PCIe) interface capable of supporting multiple high-bandwidth PCIe lanes. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

Abstract: Power consumption of CAM devices is reduced during compare operations between a search key and data stored in the device's array by reducing the amount of electric charge by which the match line is discharged during mismatch conditions. More specifically, for some embodiments, each row of the CAM array includes circuitry that discharges the match line to a virtual ground node rather than to ground potential during mismatch conditions. Because the electrical potential on the virtual ground node is greater than ground potential, power consumption associated with charging the match line back to a logic high state during the next compare operation is reduced.

Abstract: A processing system includes an interchip interface that comprises an interchip interface module having an arbiter to allocate a dedicated time slice in every fixed number of time slices, to assign a first priority to store data item(s) from a first-type channel having a first datapath width in memory during the dedicated time slice. In the remaining time slices of the fixed number of time slices, the arbiter further arbitrates among multiple channels of one or more types other than a first type, where the multiple channels correspond to at least one datapath width different from the first datapath width, and channels with wider datapath win the arbitration. The arbiter further arbitrates among two or more channels of the same type if a certain type of channel(s) wins the arbitration in a time slice. A method for implementing the same is also disclosed.

Abstract: A method and apparatus for performing half-column redundancy in a CAM device is disclosed, capable of replacing a defective half-column in the CAM array with only one half of another column. For example, present embodiments can provide twice the redundancy by replacing only one half of a defective CAM cell with one half of a spare cell or of a selected cell. The half-column redundancy disclosed herein provides finer granularity and higher effectiveness to the redundancy scheme as compared to conventional redundancy schemes employed on a CAM array. Thus, the CAM array can be designed and fabricated with a higher yield without having to accommodate for more spare columns than employed by conventional redundancy schemes, allowing for more efficient use of silicon area and a more robust CAM array design.

Abstract: An improved approach is described for implementing a clock management system. A multi-part phase locked loop circuit is provided to handle the different clock needs of the circuit, where each of the phase locked loops within the multi-part phase locked loop circuit may feed a clock output to one or more divider circuits. The divider circuits may be dedicated to specific components. For example, a SoC PLL may generate a clock output to a SoC divider that is dedicated to providing a clock to content address memory (CAM) components. This approach allows the clock management system to efficiently generate clock signals with variable levels of frequencies, even for complicated circuits having many different functional portions and components.

Abstract: A system and method are disclosed for securely transmitting and receiving a signal. A nonlinear keying modulator is used in the transmitter to encrypt the signal using a nonlinear keying modulation technique. A nonlinear keying demodulator is used in the receiver to decrypt the signal.

Abstract: Methods, systems, and circuits cancel a reflection on a channel. A main signal conditioning module improves the quality of a signal for transmission on a channel. In addition, a reflection cancellation module generates a signal that cancels reflections generated on the channel in order to improve the quality of the transmitted signal for a receiver. A summer combines an output signal from the main signal conditioning module and the reflection cancellation module.

Abstract: A CAM device is disclosed that includes an array of CAM cells in which the compare circuits of groups of CAM cells are connected together using a conductive layer interposed between a polysilicon layer of the CAM device and the metal-1 layer of the CAM device. This allows the data lines (e.g., the bit lines and/or comparand lines) of the CAM array to be formed in the metal-1 layer of the CAM device, which in turn allows the match lines of the CAM array to be formed in the metal-2 layer of the CAM device. The conductive layer, which may be a silicide layer, is connected to the match line by a via extending from the conductive layer through the metal-1 layer to the metal-2 layer.

Abstract: Disclosed is an approach for configuring devices for a multiprocessor system, where the devices pertaining to the different processors are viewed as connecting to a standardized common bus. Regardless of the specific processor to which a device is directly connected, that device can be generally identified and accessed along the standardized common bus. PCIe is an example of a suitable standardized bus type that can be employed, where the devices for each processor node are represented as PCIe devices. Therefore, each of the devices would appear to the system software as a PCIe device. A PCIe controller can then be used to access the device by referring to the appropriate device identifier. This permits any device to be accessed on any of the processor nodes, without separate and individualized configurations or drivers for each separate processor node.

Abstract: A method and system of packet assembly is provided. The method includes providing a first packet descriptor. The first packet descriptor is a pointer-to-pointer (P2P) descriptor that includes pointer information. The method further includes retrieving a first pointer referenced by the pointer information of the first packet descriptor; providing the first pointer to a DMA engine; and using the DMA engine to retrieve packet data referenced by the first pointer.

Abstract: A content addressable memory (CAM) device can include a number of bit lines. One or more of the bit lines can be connected to storage circuits of CAM cells in a corresponding column. Each CAM cell can include compare circuits that compare a stored value one or more compare data values. An isolation circuit car have a controllable impedance path connected between the bit line and a precharge voltage node and can be controlled by application of a potential at a control node. A control circuit can be coupled to the control node and can switch the isolation circuit from a high impedance state to a low impedance state prior to, and for a duration of at least of a portion of, an access operation.

Abstract: A system, method, and computer program product are provided for conditionally sending a request for data to a home node. In operation, a first request for data is sent to a first cache of a node. Additionally, if the data does not exist in the first cache, a second request for the data is sent to a second cache of the node. Furthermore, a third request for the data is conditionally sent to a home node.