Abstract: A flow of packets is communicated through a data center. The data center includes multiple racks, where each rack includes multiple network devices. A group of packets of the flow is received onto a first network device. The first device includes a neural network. The first network device generates a neural network feature vector (NNFV) based on the received packets. The first network device then sends the NNFV to a second network device. The second device uses the NNFV to determine a set of weight values. The weight values are then sent back to the first network device. The first device loads the weight values into the neural network. The neural network, as configured by the weight values, then analyzes each of a plurality of flows received onto the first device to determine whether the flow likely has a particular characteristic.

Abstract: A network device includes a Network Interface Device (NID) and multiple servers. Each server is coupled to the NID via a corresponding PCIe bus. The NID has a network port through which it receives packets. The packets are destined for one of the servers. The NID detects a PCIe congestion condition regarding the PCIe bus to the server. Rather than transferring the packet across the bus, the NID buffers the packet and places a pointer to the packet in an overflow queue. If the level of bus congestion is high, the NID sets the packet's ECN-CE bit. When PCIe bus congestion subsides, the packet passes to the server. The server responds by returning an ACK whose ECE bit is set. The originating TCP endpoint in turn reduces the rate at which it sends data to the destination server, thereby reducing congestion at the PCIe bus interface within the network device.

Abstract: A network flow processor integrated circuit includes a plurality of processors, a plurality of multi-threaded transactional memories (MTMs), and a configurable mesh posted transaction data bus. The configurable mesh posted transaction data bus includes a configurable command mesh and a configurable data mesh. Each of these configurable meshes includes crossbar switches and interconnecting links. A command bus transaction value issued by a processor can pass across the command mesh to an MTM. The command bus transaction bus value includes a reference value. The MTM uses the reference value to pull data across the configurable data mesh into the MTM. The MTM then uses the data to carry out the commanded transactional memory operation. Multiple such commands can pass across the posted transaction bus across different parts of the integrated circuit at the same time, and a single MTM can be carrying out multiple such operations at the same time.

Abstract: A pipelined run-to-completion processor includes no instruction counter and only fetches instructions either: as a result of being prompted from the outside by an input data value and/or an initial fetch information value, or as a result of execution of a fetch instruction. Initially the processor is not clocking. An incoming value kick-starts the processor to start clocking and to fetch a block of instructions from a section of code in a table. The input data value and/or the initial fetch information value determines the section and table from which the block is fetched. A LUT converts a table number in the initial fetch information value into a base address where the table is found. Fetch instructions at the ends of sections of code cause program execution to jump from section to section. A finished instruction causes an output data value to be output and stops clocking of the processor.

Abstract: An array of columns and rows of host server devices is mounted in a row of racks. Each device has a host processor and an exact-match packet switching integrated circuit. Packets are switched within the system using exact-match flow tables that are provisioned by a central controller. Each device is coupled by a first cable to a device to its left, by a second cable to a device to its right, by a third cable to a device above, and by a fourth cable to a device below. In one example, substantially all cables that are one meter or less in length are non-optical cables, whereas substantially all cables that are seven meters or more in length are optical cables. Advantageously, each device of a majority of the devices has four and only four cable ports, and connects only to non-optical cables, and the connections involve no optical transceiver.

Abstract: A system and method for handling a digital electronic flow between a first and second entity in which a flow policy is determined that is to be applied to the flow and the flow is then directed along a path in accordance with the policy. An ID is supplied for each flow and a tag associated with each flow which indicates the policy to be applied to its associated flow. Flows are also associated with one another, with associated flows having associated policies. In particular the flow may be processed or forwarded. The path may include a graph structure and virtual applications.

Abstract: The flow cache of a network flow processor (NFP) stores flow lookup information in cache lines. Some cache lines are stored in external bulk memory and others are cached in cache memory on the NFP. A cache line includes several lock/hash entry slots. Each slot can store a CAM entry hash value, associated exclusive lock status, and associated shared lock status. The head of a linked list of keys associated with the first slot is implicitly pointed to. For the other lock/entry slots, the cache line stores a head pointer that explicitly points to the head. Due to this architecture, multiple threads can simultaneously process packets of the same flow, obtain lookup information, and update statistics in a fast and memory-efficient manner. Flow entries can be added and deleted while the flow cache is handling packets without the recording of erroneous statistics and timestamp information.

Abstract: A network device includes a Network Interface Device (NID) and multiple servers. Each server is coupled to the NID via a corresponding PCIe bus. The NID has a network port through which it receives packets. The packets are destined for one of the servers. The NID detects a PCIe congestion condition regarding the PCIe bus to the server. Rather than transferring the packet across the bus, the NID buffers the packet and places a pointer to the packet in an overflow queue. If the level of bus congestion is high, the NID sets the packet's ECN-CE bit. When PCIe bus congestion subsides, the packet passes to the server. The server responds by returning an ACK whose ECE bit is set. The originating TCP endpoint in turn reduces the rate at which it sends data to the destination server, thereby reducing congestion at the PCIe bus interface within the network device.

Abstract: A transactional memory (TM) of an island-based network flow processor (IB-NFP) integrated circuit receives a Stats Add-and-Update (AU) command across a command mesh of a Command/Push/Pull (CPP) data bus from a processor. A memory unit of the TM stores a plurality of first values in a corresponding set of memory locations. A hardware engine of the TM receives the AU, performs a pull across other meshes of the CPP bus thereby obtaining a set of addresses, uses the pulled addresses to read the first values out of the memory unit, adds the same second value to each of the first values thereby generating a corresponding set of updated first values, and causes the set of updated first values to be written back into the plurality of memory locations. Even though multiple count values are updated, there is only one bus transaction value sent across the CPP bus command mesh.

Abstract: An ordering system includes a plurality of ticket order release bitmap blocks that together store a ticket order release bitmap, a bus and a Global Reordering Block (GRO). Each Ticket Order Release Bitmap Block (TORBB) stores a different part of the ticket order release bitmap. A first TORBB of the plurality of TORBBs is protected. The GRO 1) receives a queue entry onto the ordering system from a thread, 2) receives a ticket release command from the thread, and in response 3) outputs a return data of ticket release command. The queue entry includes a first sequence number. The return data of ticket release command indicates if a bit in the protected TORBB was set. An error code is included in the return data of ticket release command if a bit is set within the protected TORBB. When a bit in the TORBB is set the thread stops processing packets.

Abstract: A pipelined run-to-completion processor executes a pop stack absolute instruction. The instruction includes an opcode, an absolute pointer value, a flag don't touch bit, and predicate bits. If a condition indicated by the predicate bits is not true, then the opcode operation is not performed. If the condition is true, then the stack of the processor is popped thereby generating an operand A. The absolute pointer value is used to identify a particular register of the stack, and the content of that particular register is an operand B. The arithmetic logic operation specified by the opcode is performed using operand A and operand B thereby generating a result, and the content of the particular register is replaced with the result. If the flag don't touch bit is set to a particular value, then the flag bits (carry flag and zero flag) are not affected by the instruction execution.

Abstract: A networking device includes: 1) a first processor that includes a match table, and 2) a second processor that includes both a Flow Tracking Autolearning Match Table (FTAMT) as well as a synchronized match table. A set of multiple entries stored in the synchronized match table is synchronized with a corresponding set of multiple entries in the match table on the first processor. The FTAMT, for a first packet of the flow, generates a Flow Identifier (ID) and stores the flow ID as part of a new entry for the flow. The match of a packet to one of the synchronized entries in the synchronized match table causes an action identifier to be recorded in the new entry in the FTAMT. A subsequent packet of the flow results in a hit in the FTAMT and results in the previously recorded action being applied to the subsequent packet.

Abstract: A TCP connection is established between a client and a server, such that packets communicated across the TCP connection pass through a proxy. Based at least in part on a result of monitoring packets flowing across the TCP connection, the proxy determines whether to split the TCP control loop into two TCP control loops so that packets can be inspected more thoroughly. If the TCP control loop is split, then a first TCP control loop manages flow between the client the proxy and a second TCP control loop manages flow between the proxy and the server. Due to the two control loops, packets can be held on the proxy long enough to be analyzed. In some circumstances, a decision is then made to stop inspecting. The two TCP control loops are merged into a single TCP control loop, and thereafter the proxy passes packets of the TCP connection through unmodified.

Abstract: A network device receives TCP segments of a flow via a first SSL session and transmits TCP segments via a second SSL session. Once a TCP segment has been transmitted, the TCP payload need no longer be stored on the network device. Substantial memory resources are conserved, because the device may have to handle many retransmit TCP segments at a given time. If the device receives a retransmit segment, then the device regenerates the retransmit segment to be transmitted. A data structure of entries is stored, with each entry including a decrypt state and an encrypt state for an associated SSL byte position. The device uses the decrypt state to initialize a decrypt engine, decrypts an SSL payload of the retransmit TCP segment received, uses the encrypt state to initialize an encrypt engine, re-encrypts the SSL payload, and then incorporates the re-encrypted SSL payload into the regenerated retransmit TCP segment.

Abstract: A method involves compiling a first amount of high-level programming language code (for example, P4) and a second amount of a low-level programming language code (for example, C) thereby obtaining a first amount of native code and a second amount of native code. The high-level programming language code at least in part defines how an SDN switch performs matching in a first condition. The low-level programming language code at least in part defines how the SDN switch performs matching in a second condition. The low-level code can be a type of plugin or patch for handling special packets. The amounts of native code are loaded into the SDN switch such that a first processor (for example, x86 of the host) executes the first amount of native code and such that a second processor (for example, ME of an NFP on the NIC) executes the second amount of native code.

Abstract: A multiprocessor system includes several processors, a Shared Local Memory (SLMEM) that stores instructions and data, a system interface block, a posted transaction interface block, and an atomics block. Each processor is coupled to the system interface block via its AHB-S bus. The posted transaction interface block and the atomics block are shared resources that a processor can use via the same system interface block. A processor causes the atomics block to perform an atomic metering operation by doing an AHB-S write to a particular address in shared address space. The system interface block translates information from the AHB-S write into an atomics command, which in turn is converted into pipeline opcodes that cause a pipeline within the atomics block to perform the operation. An atomics response communicates result information which is stored into the system interface block. The processor reads the result information by reading from the same address.

Abstract: A multiprocessor system includes several processors, a prefetching instruction code interface block, a prefetching data code interface block, a Shared Local Memory (SLMEM), and Clock Gapping Circuits (CGCs). Each processor has the same address map. Each fetches instructions from SLMEM via the instruction interface block. Each accesses data from/to SLMEM via the data interface block. The interface blocks and the SLMEM are clocked at a faster rate than the processors. The interface blocks have wide prefetch lines of the width of the SLMEM. The data interface block supports no-wait single-byte data writes from the processors, and also supports no-wait multi-byte data writes. An address translator prevents one processor from overwriting the stack of another. If a requested instruction or data is not available in the appropriate prefetching circuit, then the clock signal of the requesting processor is gapped until the instruction or data can be returned to the requesting processor.

Abstract: Multiple processors share access, via a bus, to a pipelined NFA engine. The NFA engine can implement an NFA of the type that is not a DFA (namely, it can be in multiple states at the same time). One of the processors communicates a configuration command, a go command, and an event generate command across the bus to the NFA engine. The event generate command includes a reference value. The configuration command causes the NFA engine to be configured. The go command causes the configured NFA engine to perform a particular NFA operation. Upon completion of the NFA operation, the event generate command causes the reference value to be returned back across the bus to the processor.

Abstract: A method of performing an update packet sequence number packet ready command (drop packet mode operation) is described herein. A first packet ready command is received from a memory system via a bus and onto a first network interface circuit. The first packet ready command includes a multicast value. A first communication mode is determined as a function of the multicast value. The multicast value indicates a single packet was communicated by a second network interface circuit. A packet sequence number stored in a memory unit is updated. The memory unit is included in the first network interface circuit. The first network interface circuit does not free the first packet from the memory system. The network interface circuits and the memory system are included on an Island-Based Network Flow Processor. The bus is a Command/Push/Pull (CPP) bus.

Abstract: A first switch in a MPLS network receives a plurality of packets. The plurality of packets are part of a pair of flows. The first switch performs a packet prediction learning algorithm on the first plurality of packets and generates packet prediction information. The first switch communicates the packet prediction information to a Network Operation Center (NOC). In response, the NOC communicates the packet prediction information to a second switch within the MPLS network utilizing OpenFlow messaging. In a first example, the NOC communicates a packet prediction control signal to the second switch. In a second example, a packet prediction control signal is not communicated. In the first example, based on the packet prediction control signal, the second switch determines if it will utilize the packet prediction information. In the second example, the second switch independently determines if the packet prediction information is to be used.