Abstract: Addition, search, and performance of other allied activities relating to keys are performed in a hardware hash table. Further, high performance and efficient design may be provided for a hash table applicable to CPU caches and cache coherence directories. Set-associative tables and cuckoo hashing are combined for construction of a directory table of a directory based cache coherence controller. A method may allow configuration of C cuckoo ways, where C is an integer greater than or equal to 2, wherein each cuckoo way Ci is a set-associative table with N sets, where each set has an associativity of A, where A is an integer greater than or equal to 2.

Abstract: The present disclosure is directed to hardware hash tables, and more specifically, to generation of a cache coherent system such as in a Network on Chip (NoC). The present disclosure is further directed to a directory structure that includes a new field, referred to, for instance as, encoded value, which indicates the original owner of a dirty line. As an original holder may have held or modified the original line, by tracking the original holder, example implementations can track the agents that are potentially dirty, as the encoded value can indicate the agent with the most recently unique line, which can then be shared with the other agents.

Abstract: Systems and methods described herein are directed to solutions for Network on Chip (NoC) interconnects that automatically and dynamically determines the position of hosts of various size and shape in a NoC topology based on the connectivity, bandwidth and latency requirements of the system traffic flows and certain performance optimization metrics such as system interconnect latency and interconnect cost. The example embodiments selects hosts for relocation consideration and determines a new possible position for them in the NoC based on the system traffic specification, shape and size of the hosts and by using probabilistic function to decide if the relocation is carried out or not. The procedure is repeated over new sets of hosts until certain optimization targets are satisfied or repetition count is exceeded.

Abstract: Systems and methods described herein are directed to solutions for NoC interconnects that provide end-to-end uniform- and weighted-fair allocation of resource bandwidths among various contenders. The example implementations are fully distributed and involve tagging the messages with meta-information when the messages are injected in the interconnection network. Example implementations may involve routers using various arbitration phases, and making local arbitration decisions based on the meta-information of incoming messages. The meta-information can be of various types based on the number of router arbitration phases, and the desired level of sophistication.

Abstract: Systems and methods for automatically generating a Network on Chip (NoC) interconnect architecture with pipeline stages are described. The present disclosure includes example implementations directed to automatically determining the number and placement of pipeline stages for each channel in the NoC. Example implementations may also adjust the buffer at one or more routers based on the pipeline stages and configure throughput for virtual channels.

Abstract: Systems and methods described herein are directed to solutions for Network on Chip (NoC) interconnects that automatically and dynamically determines the topology of different NoC layers and maps system traffic flows to various routes in various NoC layers that satisfies the latency requirements of the flows. The number of layers and their topology is dynamically allocated and optimized by performing load balancing of the traffic flows between the channels and routes of different NoC layers and updating the topology of the NoC layers as they are mapped. In addition to allocating additional NoC layers and topologies to satisfy the latency requirements of the flows, the NoC layers and topologies may also be allocated to satisfy the bandwidth requirements of the flows or to provide the additional virtual channels that may be needed for deadlock avoidance and to maintain the isolation properties between various flows.

Abstract: The present disclosure is directed to systems and methods for connecting hosts to any router by the use of bridges. Example implementations described herein are directed to determining connections between routers and hosts based on the topology of the NoC and cost functions. Unused routers may also be removed from the NoC configuration and unused directional host ports of routers may be utilized to connect hosts together depending on a cost function and the desired implementation.

Abstract: Systems and methods described herein are directed to solutions for Network on Chip (NoC) interconnects that automatically and dynamically determines the number of layers needed in a NoC interconnect system based on the bandwidth requirements of the system traffic flows. The number of layers is dynamically allocated and minimized by performing load balancing of the traffic flows between the channels and routes of different NoC layers as they are mapped. Additional layers may be allocated to provide the additional virtual channels that may be needed for deadlock avoidance and to maintain the isolation properties between various system flows. Layer allocation for additional bandwidth and additional virtual channels (VCs) may be performed in tandem.

Abstract: Example implementations described herein are directed to automatically determine an optimal NoC topology using heuristic based optimizations. First, an optimal orientation of ports of various hosts is determined based on the system traffic and connectivity specification. Second, the NoC routers to which the host's port are directly connected to are determined in the NoC layout. Third, an optimal set of routes are computed for the system traffic and the required routers and channels along the routes are allocated forming the full NoC topology. The three techniques can be applied in any combination to determine NoC topology, host port orientation, and router connectivity that reduces load on various NoC channels and improves latency, performance, and message transmission efficiency between the hosts.

Abstract: The present application is directed to a control circuit that provides a directory configured to maintain a plurality of entries, wherein each entry can indicate sharing of resources, such as cache lines, by a plurality of agents/hosts. Control circuit of the present invention can further provide consolidation of one or more entries having a first format to a single entry having a second format when resources corresponding to the one or more entries are shared by the agents. First format can include an address and a pointer representing one of the agents, and the second format can include a sharing vector indicative of more than one of the agents. In another aspect, the second format can utilize, incorporate, and/or represent multiple entries that may be indicative of one or more resources based on a position in the directory.

Abstract: Systems and methods described herein are directed to solutions for NoC interconnects that provide end-to-end uniform- and weighted-fair allocation of resource bandwidths among various contenders. The example implementations are fully distributed and involve computing weights for various channels in a network on chip (NoC) based on the bandwidth requirements of flows at the channels. Example implementations may involve using the weights to perform weighted arbitration between channels in the NoC to provide quality of service (QoS). The weights may be adjusted dynamically by monitoring the activity of flows at the channels. The newly adjusted weights can be used to perform the weighted arbitrations to avoid unfair bandwidth allocations.

Abstract: Systems and methods for automatically building a deadlock free inter-communication network in a multi-core system are described. The example implementations described herein involve a high level specification to capture the internal dependencies of various cores, and using it along with the user specified system traffic profile to automatically detect protocol level deadlocks in the system. When all detected deadlock are resolved or no such deadlocks are present, messages in the traffic profile between various cores of the system may be automatically mapped to the interconnect channels and detect network level deadlocks. Detected deadlocks then may be avoided by re-allocation of channel resources. An example implementation of the internal dependency specification and using it for deadlock avoidance scheme is presented on Network-on-chip interconnects for large scale multi-core system-on-chips.

Abstract: Example implementations are directed to more efficiently delivering a multicast message to multiple destination components from a source component. Multicast environment is achieved with transmission of a single message from a source component, which gets replicated in the NoC during routing towards the destination components indicated in the message. Example implementations further relate to an efficient way of implementing multicast in any given NoC topology, wherein one or more multicast trees in the given NoC topology are formed and one of these trees are used for routing a multicast message to its intended destination components mentioned therein.

Abstract: Systems and methods described herein are directed to solutions for Network on Chip (NoC) interconnects that supports reconfigurability to support a variety of different traffic profiles each having different sets of traffic flows after the NoC is designed and deployed in a SoC. Reconfiguration of the NoC to map and load a new traffic profile or change the currently mapped traffic profile is performed by an external optimization module which maps various transactions of a given traffic profile to the NoC and reconfigure the NoC hardware by loading the computed mapping information. As part of the mapping process, load balancing between NoC layers may be performed by automatically assigning the transactions in the traffic profile to be routed over certain NoC layers and channels, automatically determining the routes based on the bandwidth requirements of the transaction. The deadlock avoidance and isolation properties of various transactions are maintained during the mapping.

Abstract: Systems and methods involving construction of a system interconnect in which different channels have different widths in numbers of bits. Example processes to construct such a heterogeneous channel NoC interconnect are disclosed herein, wherein the channel width may be determined based upon the provided specification of bandwidth and latency between various components of the system.

Abstract: Example implementations described herein are directed to a floor plan for a Network on Chip (NoC) topology that can include a plurality of on chip blocks of substantially non-uniform shapes and dimensions. An interconnection network is synthesized along with a plan for a physical layout of the interconnection network based on physical dimensions of the plurality of on chip blocks, the physical dimensions of the floorplan and relative placement information for placing the plurality of on chip blocks on the floorplan. Porosity information for the plurality of on chip blocks on the floorplan and required chip functionality may also be taken into consideration.

Abstract: Example implementations described herein are directed to a system on chip (SoC) that can include a plurality of blocks of substantially non-uniform shapes and dimensions, a plurality of routers, and a plurality of links between routers. The plurality of blocks and the plurality of routers are interconnected by the plurality of links using a Network-on-Chip (NoC) architecture with a sparse mesh topology. The sparse mesh topology involves a sparsely populated mesh which is a subset of a full mesh having one or more of the plurality of routers or links removed. The plurality of blocks communicate among each other by routing messages over the remaining ones of the plurality of routers and links of the sparse mesh.

Abstract: Systems and methods described herein are directed to solutions for NoC interconnects that provide end-to-end uniform- and weighted-fair allocation of resource bandwidths among various contenders. The example implementations are fully distributed and involve computing weights for various channels in a network on chip (NoC) based on the bandwidth requirements of flows at the channels. Example implementations may involve using the weights to perform weighted arbitration between channels in the NoC to provide quality of service (QoS). The weights may be adjusted dynamically by monitoring the activity of flows at the channels. The newly adjusted weights can be used to perform the weighted arbitrations to avoid unfair bandwidth allocations.

Abstract: Systems and methods for automatically building a deadlock free inter-communication network in a multi-core system are described. The example implementations described herein involve a high level specification to capture the internal dependencies of various cores, and using it along with the user specified system traffic profile to automatically detect protocol level deadlocks in the system. When all detected deadlock are resolved or no such deadlocks are present, messages in the traffic profile between various cores of the system may be automatically mapped to the interconnect channels and detect network level deadlocks. Detected deadlocks then may be avoided by re-allocation of channel resources. An example implementation of the internal dependency specification and using it for deadlock avoidance scheme is presented on Network-on-chip interconnects for large scale multi-core system-on-chips.

Abstract: Systems and methods described herein are directed to solutions for NoC interconnects that provide end-to-end uniform- and weighted-fair allocation of resource bandwidths among various contenders. The example implementations are fully distributed and involve tagging the messages with meta-information when the messages are injected in the interconnection network. Example implementations may involve routers using various arbitration phases, and making local arbitration decisions based on the meta-information of incoming messages. The meta-information can be of various types based on the number of router arbitration phases, and the desired level of sophistication.