Abstract: An adaptive forward error correction (FEC) protocol for use in an asynchronous transfer mode (ATM) communication network is provided. Whether a feasibility condition is met indicating that FEC can compensate for an expected number of burst errors in a FEC encoded payload is determined. Subsequently, FEC encoding is performed on protocol data units (PDUs) within a payload to form the FEC encoded payload only when the feasibility condition is met. Adaptive FEC sending and receiving units which effectuate the adaptive FEC protocol are provided. In addition, an alternative adaptive FEC protocol is provided which determines a feasibility condition based on whether a PDU loss probability between connection service application points for a payload is greater than an effective PDU loss probability for the payload with associated FEC PDUs at a given load on the communication network. Also, a method for determining an overhead parameter for adaptive FEC in a communication network is provided.

Abstract: A control program for IBM compatible microprocessors utilizing the MSDOS operating system provides the ability for a plurality of application programs to pass information amongst themselves and to a KERNEL program whereby the KERNEL may spawn applications according to the contents of its message buffers, thereby enhancing the MSDOS environment without the usually encountered conflicts associated with inter-programmed communication schemes.

Abstract: A circuit board capable of live-insertion or hot-swapping into a live chassis backplane. The circuit board is provided with a power control circuitry for gracefully ramping up board power after insertion, or gracefully removing power just prior to physical removal of a circuit board from the board slot. A pair of ejector levers are provided on each side of the circuit board. A push button switch is provided proximate one ear thereof and is selectively opened or closed depending upon the position of an ejector cover which can be secured thereover in an interlocking relationship. Upon retraction of the extractor cover, the switch is opened, and the converse applies. Power MOSFETs are provided between the card edge and the board power busses which are gracefully turned on and off as a function of the switch position. A high-side gate driver provides an increased bias voltage, which bias voltage is communicated through the closed switch to the gates of the MOSFETs.

Abstract: A jitter measurement system for a serial digital data link includes a clock recovery element effective to separate a clock signal from the digital data bits being transmitted. The clock signal is applied first to a programmable delay element whose output is applied to as a first input to a decision circuit. The second input to the decision is the serial data stream. The relation of the data to the clock is initially set so that the clock is sampling the data at approximately the transition point of the data. Depending on the exact location of the data relative to the clock signal, the result of the sampling process will yield one of two results. First, if the data transition occurs before the clock transition, no error results. However, if the clock transition occurs before the data transition, an error results. An error ratio detector circuit determines an error ratio which is compared to a predetermined reference.

Abstract: A method and apparatus for deterministic access to a carrier-sense-multiple-access (CSMA) or carrier-sense-multiple-access with collision detection (CSMA/CD) local area network (LAN) alters the basic indeterminate contention algorithm of the CSMA/CD protocol LAN within a hub controller. The hub controller includes media control logic that can selectively raise a pseudo carrier control signal to each port, thereby inhibiting any CSMA/CD protocol LAN transmissions by that port. In this way, the media control logic allows the hub controller to control which of the multiple ports will be allowed to contend for access to a common internal bus within the hub controller and for how long. A variety of different deterministic contention algorithms can be implemented by the hub controller, such as sequential polling, interrupt allocation, or a combination of deterministic contention algorithms with the normal CSMA/CD indeterminate contention algorithm.

Abstract: A seamless clock distribution scheme for a system incorporating sequential digital logic devices disposed on multiple parallel boards for reducing or substantially eliminating skew. The multiple parallel boards are positioned on and project outward from one side of a centerplane. A single clock board, generating multiple copies of the system clock and mounted at a right angle to the parallel boards on the opposite side of the centerplane are connected by shared pins passing through apertures formed in the centerplane. This shared pin connection allows for simple, though near-ideal transmission of the clock signal copies between the parallel logic boards and the clock board with a minimum mismatch of the clock signal between two parallel boards.

Abstract: A network communications adapter interconnects a plurality of digital computing resources for mutual data exchange in which a high performance, large capacity common memory is provided with a pair of external buses which allows multiple processors to store information in and read information from the common memory. The common memory is configured into two banks, each bank operating independently and concurrently under control of bus switching logic with separate address, control and data buses. The common memory typically provides 400 megabits per second of bandwidth to the multiple attached thirty-two and sixteen bit processors which may be coupled either to both buses simultaneously or individually to the two buses. The bus switching logic then allocates all of the available bandwidth to the individual processors coupled to the buses based upon a predetermined profile established at the time of system installation. Also included in the bus switch logic is circuitry for broadcasting a processor I.D.

Abstract: A time-division multiplexed, data communications system allowing multiple user devices, including super computer buses configured in a local network, and other existing network hierarchies to exchange digital data over extended distances at speeds heretofore unattainable. The system includes a plurality of intelligent nodes, termed "DATApipe.TM. adapters", which are coupled to a fiber optic bus. The DATApipe adapters function as interface devices between the fiber optic bus and the I/O processors which are used to couple the user devices and networks to the DATApipe adapters.

Abstract: A transceiver (transmitter-receiver) for high frequency data pulse signals is connected to a coaxial cable transmission line through a distributed delay line which has an impedance equal in value to the characteristic impedance of the coaxial cable transmission line. The transceiver transmitting and receiving circuits are tapped into the transmission line and form a part of the distributed delay line. When not in the transmitting mode, the transmitter circuit appears as a reactive element of the distributed delay line and thereby introduces minimum loss or reflection into the transmission line. The transmission line can serve as a trunk line for a number of transceivers by permitting virtually unrestricted multipoint connections to the line.