Abstract: A method for interacting with quantum states over respective time intervals comprises: providing, from at least one optical fiber interface, a fiber-coupled optical mode that controls optical coupling to and/or from an optical fiber, where at least a portion of the optical fiber extends outside of an interior of a housing comprising the at least one optical fiber interface; providing a quantum state from each quantum state emission element (QSEE) housed on or inside the housing; providing, from each of multiple portions of one or more directional structures, a preferential direction for an associated element-coupled optical mode that controls optical coupling to and from a different respective subset of one or more of the QSEEs; and scanning a scanning structure housed on or inside the housing to change an overlap between the fiber-coupled optical mode and a different respective one of the element-coupled optical modes over each time interval.

Abstract: A discrete wearable device having a tactile switch, wireless connection capabilities, and is integrated with a personal security, concierge, or service system. The device integrates with accessories such as personal articles like zippers and bra straps and with containers such as a case, cover, or jewelry locket. The device connects to a first responder and automatically launches a smart device application with the push of the tactile switch.

Abstract: A protector module for use with a communication system, such as a telephone system having a tip line and a ring line, includes a base member and a plurality of electrically conductive pins mounted on the base member. A first electrical contact is fixedly mounted on the top surface of the base member and is in electrical communication with one of the tip line and the ring line. A movable second electrical contact is connected to a ground pin mounted on the base member and is situated in alignment with the first electrical contact. A solder pellet, which may melt in high current, long duration power surges, and a solid state device, are positioned between the first and second electrical contacts.

Abstract: A network application may be run on a host computer using a target protocol stack by launching a network application on the host computer, opening a target protocol stack library on the host computer before opening a host computer system library and using the target protocol stack library to divert interface calls associated with the network application to a target protocol stack, whereby the network application runs on the host computer as if it were running directly on a computer on which the target protocol stack is available. A network environment may be simulated including wireless communication between a plurality of mobile devices. Multiple instances of the target protocol stack library may be opened to divert interface calls associated with the network application to the target protocol stack. A hardware test bed may be emulated to which the network application may be applied.

Abstract: Systems and methods for performing high-speed multi-channel forward error correction using external DDR SDRAM is provided. According to one exemplary aspect, an interleaver/deinterleaver performs both read and write accesses to the DDR SDRAM that are burst-oriented by hiding active and precharge cycles in order to achieve high data rate operations. The interleaver/deinterleaver accesses data in the DDR SDRAM as read blocks and write blocks. Each block includes two data sequences. Each data sequence further includes a predetermined number of data words to be interleaved/deinterleaved. The PRECHARGE and ACTIVE command for one data sequence is issued when a preceding data sequence is being processed. Data in one read/write data sequence has the same row address within the same bank of the DDR SDRAM.

Abstract: Efficient synchronization techniques that support multiple reference clocks in an EQAM device. Consider a plurality of different modulators in the EQAM device receiving data from a corresponding plurality of different sources having corresponding different timing references (i.e., different source reference clocks). To accommodate this, the modulators all operate using a common system clock, and each modulator is provided with a phase synchronizer. The phase synchronizer synchronizes the modulated symbol phases to the corresponding reference clock.

Abstract: Efficient synchronization techniques that support multiple reference clocks in an EQAM device. Consider a plurality of different modulators in the EQAM device receiving data from a corresponding plurality of different sources having corresponding different timing references (i.e., different source reference clocks). To accommodate this, the modulators all operate using a common system clock, and each modulator is provided with a phase synchronizer. The phase synchronizer synchronizes the modulated symbol phases to the corresponding reference clock.

Abstract: A method for managing UMA communications within a local area network and a network controller are disclosed. The method includes establishing a first connection between a first UMA device and a LAN-based UMA network controller (LAN-UNC) and establishing a second connection between a second UMA device and the LAN-UNC. The first and second connections are carried over the local area network. The first and second UMA devices are connected to the same local area network. The method provides establishing a third connection between the LAN-UNC and a UMA network controller (UNC). The UNC is connected to an external network and the third connection extends over the external network. The method includes transporting packets received using the first and second connections to the UNC using the third connection. Packets received using the third connection are transported to the first UMA device using the first connection and to the second UMA device using the second connection.

Abstract: Systems and methods for performing high-speed multi-channel forward error correction using external DDR SDRAM is provided. According to one exemplary aspect, an interleaver/deinterleaver performs both read and write accesses to the DDR SDRAM that are burst-oriented by hiding active and precharge cycles in order to achieve high data rate operations. The interleaver/deinterleaver accesses data in the DDR SDRAM as read blocks and write blocks. Each block includes two data sequences. Each data sequence further includes a predetermined number of data words to be interleaved/deinterleaved. The PRECHARGE and ACTIVE command for one data sequence is issued when a preceding data sequence is being processed. Data in one read/write data sequence has the same row address within the same bank of the DDR SDRAM.

Abstract: Methods, apparatuses, and systems are presented for switching between channels of encoded media data involving receiving encoded media data including reference frames and dependent frames for a plurality of channels, wherein each dependent frame refers to at least one reference frame. Frames associated with a first channel from the plurality of channels are decoded to generate a decoded signal for the first channel. While decoding frames associated with the first channel, data corresponding to at least one reference frame associated with a second channel from the plurality of channels are stored. In response to a control signal for switching from the first to the second channel, at least one dependent frame associated with the second channel is decoded by utilizing the stored data corresponding to the at least one reference frame associated with the second channel, to generate a decoded signal for the second channel.

Abstract: Systems and methods for performing high-speed multi-channel forward error correction using external DDR SDRAM is provided. According to one exemplary aspect, an interleaver/deinterleaver performs both read and write accesses to the DDR SDRAM that are burst-oriented by hiding active and precharge cycles in order to achieve high data rate operations. The interleaver/deinterleaver accesses data in the DDR SDRAM as read blocks and write blocks. Each block includes two data sequences. Each data sequence further includes a predetermined number of data words to be interleaved/deinterleaved. The PRECHARGE and ACTIVE command for one data sequence is issued when a preceding data sequence is being processed. Data in one read/write data sequence has the same row address within the same bank of the DDR SDRAM.

Abstract: A distributed computing bus that provides both data transport and ambient computing power is provided. Contemplated buses comprise a network fabric of interconnected networking infrastructure nodes capable of being programmed before or after installation in the field. A fabric manager organizes the fabric into a bus topology communicatively coupling computing elements that exchange payload data using a bus protocol. Nodes within the bus topology operate on the payload data as the data passes through the node on route to its destination.

Abstract: A device and method for canceling or attenuating harmonics noise without distorting the incoming signal. An exemplary device includes the use of an estimation loop to generate an artificial signal to eliminate or attenuate the influence of harmonics. The estimation loop includes a mixer adapted to produce a mixed signal by processing or combining the incoming signal and the artificial signal. The estimation loop includes an error detector, a low-pass filter, a parameter estimator, and a numerically controlled oscillator. The parameter estimator produces information relating to the phase, frequency, and amplitude of an incoming harmonics spur and will be used by the numerically controlled oscillator to generate the artificial signal. If the mixed signal contains relatively low levels of harmonics residuals, the mixed signal is produced at the output in lieu of the incoming signal.

Abstract: A system and method for network simulation and enhancement includes an experiment configuration engine that provides various proposed traffic and/or network models, and a simulator responsive to the proposed traffic and/or network models to execute a plurality of simulations for the network using parallel discrete event simulation, to determine an optimal network configuration based upon an objective function for enhancing an aspect of network performance. The traffic and/or network models may be based on monitored data from the network indicating a current network state and current network traffic. Reconfiguration instructions for the new network configuration may be conveyed from the simulator to the network, so as to effectuate ongoing, real-time enhancement of the network. The network model(s) may cover internal operational details of individual network devices (e.g., routers and/or switches) as well as operation of the network as a whole.

Abstract: An MPEG processor is provided. According to one aspect of the processor, multiple MPEG data streams for corresponding channels are individually stored in an off-chip memory. Corresponding data for a channel is then retrieved from the off-chip memory for processing. The retrieved data is then decoded. The decoded results and associated information are stored on the off-chip memory. Some or all of the associated information that can be used for decoding subsequent data is stored in an on-chip memory. When video images need to be displayed, the corresponding data that is needed for that purpose is then retrieved from the off-chip memory and provided to an analog encoder for encoding in a format that is compatible with an analog display device.

Abstract: A decoder includes a transport engine configured to receive programs and extract timing information and timestamps embedded in the programs. An adder is configured to add a set of timing offsets to the sets of timing information to adjust the timing information from a first time basis to a second time basis. Sums of the timing offsets and the timing information are referred to the mapped-timing information. A correction engine is configured to update the timing offsets as timing information is encountered in the programs, and an offset register is configured to: receive the timing offsets, store the timing offsets, and transfer the timing offsets to the adder. The adder is also configured to add the timing offsets to the timestamps to adjust the time basis of the timestamps from the first time basis to the second time basis. A program is decoder configured to receive the adjusted timestamps to decode the programs.

Abstract: A system for high-speed access and recording includes a demodulator, a buffer memory, and a hard disk. During a write cycle, a content stream is stored in buffer memory and thereafter transferred to the demodulator. When the buffer memory reaches its storage capacity, its contents are transferred to the hard disk for storage. During a read cycle, contents from the hard disk are read and then stored in the buffer memory. The hard disk further includes includes a high-speed zone and a random-access zone, which are configured to operate in a high-speed mode, a random-access mode, and a buffer-cleaning mode.

Abstract: A system for optimizing bandwidth of a video-on-demand system is provided. According to one aspect of the system, upon receiving a request from a first subscriber for a program, the system delivers the program to the first subscriber via a first communication channel. Upon receiving a request from a second subscriber for the same program, the system delivers only a beginning portion of the program to the second subscriber via a second communication channel and at the same time records a remaining portion of the program from the first communication channel. At the appropriate time, the recorded remaining portion of the program are shown to the second subscriber.

Abstract: A distributed computing system comprising networking infrastructure and methods of executing an application on the distributed computing system is presented. Interconnected networking nodes offering available computing resources form a network fabric. The computing resources can be allocated from the networking nodes, including available processing cores or memory elements located on the networking nodes. A software application can be stored in a system memory comprising memory elements allocated from the nodes. The software application can be disaggregated into a plurality of executable portions that are striped across the allocated processing cores by assigning each core a portion to execute. When the cores are authenticated with respect to their portions, the cores are allowed to execute the portions by accessing the system memory over the fabric. While executing the software application, the networking nodes having the allocated cores concurrently forward packets through the fabric.

Abstract: A managed surface-space network fabric is presented. The surface-space network fabric can include a spaced-based network fabric and a surface-based network fabric integrated together to form a single fabric managed by a global fabric manager. The global fabric manager cooperates with other fabric managers local to each fabric to establish a communication topology among all the nodes of the fabric. Preferred topologies include paths from any port on a node to any other port on another node in the fabric. The surface-space fabric, and each individual fabric, can function as a distributed core fabric operating as a single, coherent device.