Abstract: In some embodiments, an integrated circuit may include a substrate and a memory array disposed on the substrate, where the memory array includes a plurality of discrete memory banks. The integrated circuit may also include a processing array disposed on the substrate, where the processing array includes a plurality of processor subunits, each one of the plurality of processor subunits being associated with one or more discrete memory banks among the plurality of discrete memory banks. The integrated circuit may also include a controller configured to implement at least one security measure with respect to an operation of the integrated circuit and take one or more remedial actions if the at least one security measure is triggered.

Abstract: Distributed processors and methods for compiling code for execution by distributed processors are disclosed. In one implementation, a distributed processor may include a substrate; a memory array disposed on the substrate; and a processing array disposed on the substrate. The memory array may include a plurality of discrete memory banks, and the processing array may include a plurality of processor subunits, each one of the processor subunits being associated with a corresponding, dedicated one of the plurality of discrete memory banks. The distributed processor may further include a first plurality of buses, each connecting one of the plurality of processor subunits to its corresponding, dedicated memory bank, and a second plurality of buses, each connecting one of the plurality of processor subunits to another of the plurality of processor subunits.

Abstract: Distributed processors and methods for compiling code for execution by distributed processors are disclosed. In one implementation, a distributed processor may include a substrate; a memory array disposed on the substrate; and a processing array disposed on the substrate. The memory array may include a plurality of discrete memory banks, and the processing array may include a plurality of processor subunits, each one of the processor subunits being associated with a corresponding, dedicated one of the plurality of discrete memory banks. The distributed processor may further include a first plurality of buses, each connecting one of the plurality of processor subunits to its corresponding, dedicated memory bank, and a second plurality of buses, each connecting one of the plurality of processor subunits to another of the plurality of processor subunits.

Abstract: A memory chip may include: a plurality of memory banks; a data storage configured to store access information indicative of access operations for one or more segments of the plurality of memory banks; and a refresh controller configured to perform a refresh operation of the one or more segments based, at least in part, on the stored access information.

Abstract: In some embodiments, an integrated circuit may include a substrate and a memory array disposed on the substrate, where the memory array includes a plurality of discrete memory banks. The integrated circuit may also include a processing array disposed on the substrate, where the processing array includes a plurality of processor subunits, each one of the plurality of processor subunits being associated with one or more discrete memory banks among the plurality of discrete memory banks. The integrated circuit may also include a controller configured to implement at least one security measure with respect to an operation of the integrated circuit and take one or more remedial actions if the at least one security measure is triggered.

Abstract: A system for distributed storage agents includes at least one memory and at least one compute node comprising at least one agent module. The at least one agent module is configured to cause at least a portion of data stored in the at least one memory to be pushed to a destination in accordance with an agent access plan.

Abstract: A memory chip may include: a plurality of memory banks; a data storage configured to store access information indicative of access operations for one or more segments of the plurality of memory banks; and a refresh controller configured to perform a refresh operation of the one or more segments based, at least in part, on the stored access information.

Abstract: A memory chip may include: a plurality of memory banks; a data storage configured to store access information indicative of access operations for one or more segments of the plurality of memory banks; and a refresh controller configured to perform a refresh operation of the one or more segments based, at least in part, on the stored access information.

Abstract: Disclosed embodiments include a computational memory system. The computational memory system includes at least one computational memory chip including one or more processor subunits and one or more memory banks formed on a common substrate. The at least one computational memory chip is configured to store one or more portions of an embedding table in the one or more memory banks, the embedding table including one or more feature vectors. The one or more processor subunits are configured to receive a sparse vector indicator from a host external to the at least one computational memory chip and, based on the received sparse vector indicator and the one or more portions of the embedding table, generate one or more vector sums.

Abstract: Disclosed embodiments include a computational memory system. The computational memory system includes at least one computational memory chip including one or more processor subunits and one or more memory banks, formed on a common substrate. The computational memory system also includes at least one local error correction code (ECC) module configured for calculating an original ECC based on received data, at least one local ECC module associated with at least one of the processor subunits and/or at least one of the memory banks.

Abstract: Disclosed embodiments include a processing system. The processing system includes an internal element including a slave controller. The processing system also includes a master controller configured for communication with the internal element. the internal element is configured to activate an error indication via an alert channel to the master controller responsive to an error signal from the slave controller. Further, the internal element is configured to activate a data ready indication via the alert channel responsive to a data ready signal from the slave controller.

Abstract: An information transfer system may include: a master controller (XMC) configured to issue a command in the form of a memory protocol data packet, and wherein the master controller is configured to generate routing information indicating whether the memory protocol data packet is to be processed according to a first protocol or according to a second protocol different from the first protocol. The information transfer system may also include a slave controller (XSC) configured to receive the memory protocol data packet from the master controller, wherein the slave controller is configured to use the routing information to selectively cause the memory protocol data packet to be processed according to the first protocol or according to the second protocol.

Abstract: Disclosed embodiments include a computational memory system. The computational memory system includes a master controller configured to receive a configuration function from a host CPU and convert the received configuration function into one or more lower level configuration functions. The computational memory system also includes at least one computational memory chip, wherein the at least one computational memory chip includes a plurality of processor subunits and a plurality of memory banks formed on a common substrate. The master controller is adapted to configure the at least one computational memory chip using the one or more lower level configuration functions.

Abstract: Disclosed embodiments include a data processing unit. The data processing unit includes a data analysis unit configured to acquire a plurality of data elements from a memory, evaluate each of the plurality of data elements relative to at least one criteria, and generate an output that includes a plurality of validity indicators identifying a first plurality of data elements among the plurality of data elements that validly satisfy the at least one criteria and identifying a second plurality of data elements among the plurality of data elements that do not validly satisfy the criteria. The data processing unit also includes a data packer configured to generate, based on the output of the data analysis unit, a packed data output including the first plurality of data elements and omitting the second plurality of data elements.

Abstract: Disclosed embodiments include a data filter system including an interface and data filter circuitry. The data filter circuitry is configured to receive a data filter initiation signal via the interface, and in response to receipt of the data filter initiation signal, perform at least one operation associated with a data query, wherein the data query implicates a body of data stored in at least one storage unit; wherein performance of the at least one operation associated with the data query results in generation of a filtered data subset from the body of data, including less data than the body of data implicated by the data query; and transfer the filtered data subset to a host processor configured to perform one or more additional operations relative to the data query to generate an output to the data query.

Abstract: Disclosed embodiments include system including a hardware based, programmable data analytics processor configured to reside between a data storage unit and one or more hosts. The programmable data analytics processor includes a selector module configured to input a first set of data and, based on a selection indicator, output a first subset of the first set of data; a filter and project module configured to input a second set of data and, based on a function, output an updated second set of data; a join and group module configured to combine data from one or more third data sets into a combined data set; and a communications fabric configured to transfer data between any of the selector module, the filter and project module, and the join and group module.

Abstract: Disclosed embodiments include an accelerated database management system including at least one processor including circuitry and a memory. The memory includes instructions that when executed by the circuitry cause the at least one processor to: receive an initial database query; generate a main query based on the initial database query; analyze the main query, and based on the analysis of the main query, generate at least a first sub-query and a second sub-query, wherein the second sub-query differs from the first sub-query; process the first sub-query along a first processing path to provide a first input to an execution module; process the second sub-query along a second processing path, different from the first processing path, to provide a second input to the execution module; and based on the first input and the second input received by the execution module, generate a main query result.

Abstract: A data pre-processing architecture may include an interface and a pruning logic configured to receive, via the interface, at least one filter value from a query processor; use the at least one filter value to scan rows or columns of a data table stored in a memory; generate a selection indicator identifying a set of rows or columns of the data table where the at least one filter value resides; and provide to the query processor a filtered output based on the selection indicator.

Abstract: A memory chip may include: a plurality of memory banks; a data storage configured to store access information indicative of access operations for one or more segments of the plurality of memory banks; and a refresh controller configured to perform a refresh operation of the one or more segments based, at least in part, on the stored access information.

Abstract: In some embodiments, an integrated circuit may include a substrate and a memory array disposed on the substrate, where the memory array includes a plurality of discrete memory banks. The integrated circuit may also include a processing array disposed on the substrate, where the processing array includes a plurality of processor subunits, each one of the plurality of processor subunits being associated with one or more discrete memory banks among the plurality of discrete memory banks. The integrated circuit may also include a controller configured to implement at least one security measure with respect to an operation of the integrated circuit and take one or more remedial actions if the at least one security measure is triggered.