Abstract: A method and apparatus for analyzing side-channel security vulnerabilities in a digital device. A first time sequence of measurements of side-channel related phenomena of the digital device, such as power draw or electromagnetic emissions is obtained. A second time sequence of debug outputs of the digital device, such as program counter contents or other device processor or register states, is obtained. The first time sequence and the second time sequence are obtained based on a common time reference, and thus correlated in time. A controller can provide a common timing signal to measurement equipment obtaining the first time sequence and to a debug tool obtaining the second time sequence, and the common time reference can be correspond to the common timing signal.
Type:
Grant
Filed:
October 6, 2020
Date of Patent:
November 7, 2023
Assignee:
Newae Technology Inc
Inventors:
Jean-Pierre Thibault, Colin Patrick O'Flynn
Abstract: Methods and apparatus are provided for determining if an embedded system or integrated circuit is operating correctly, or if the device is faulty or counterfeit. Measurements of power consumption are used to determine the state of the device under test, these measurements being performed at multiple operating or environmental conditions to increase the ability of the apparatus to detect faulty and counterfeit devices.
Abstract: Methods and apparatus are provided for causing the incorrect operation (‘faults’) of digital devices such as embedded computer systems or integrated circuits. The apparatus uses a switching element to cause perturbations on the power supplies of the digital device. This apparatus can be connected to existing embedded systems with a minimal of modifications, and can insert a variety of faults into those embedded systems. Such faults can be used for verification of fault-tolerant systems or algorithms, including both safety-critical designs and cryptographic designs.