Abstract: Apparatus and methods for variable capacitor arrays are provided herein. In certain configurations, an apparatus includes a variable capacitor array and a bias voltage generation circuit. The variable capacitor array includes a plurality of metal oxide semiconductor (MOS) variable capacitor cells, which include one or more pairs of MOS capacitors implemented in anti-parallel and/or anti-series configurations. In certain implementations, the MOS variable capacitor cells are electrically connected in parallel with one another between a radio frequency (RF) input and an RF output of the variable capacitor array. The bias voltage generation circuit generates bias voltages for biasing the MOS capacitors of the MOS variable capacitor cells.

Abstract: Techniques for implementing tunable lumped element filters with transmission line sections. Transmission lines sections are used to implement one or more inductive or capacitance component elements of the filter. The filter is tunable by changing the dielectric constants of the transmission lines. In particular implementations there is an individual transmission line section for each lumped element component of a filter. Different filter circuits may be combined to provide a universal tunable filter assembly.

Abstract: Apparatus and methods for variable capacitor arrays are provided herein. In certain configurations, an apparatus includes a variable capacitor array and a bias voltage generation circuit. The variable capacitor array includes a plurality of metal oxide semiconductor (MOS) variable capacitor cells, which include one or more pairs of MOS capacitors implemented in anti-parallel and/or anti-series configurations. In certain implementations, the MOS variable capacitor cells are electrically connected in parallel with one another between a radio frequency (RF) input and an RF output of the variable capacitor array. The bias voltage generation circuit generates bias voltages for biasing the MOS capacitors of the MOS variable capacitor cells.

Abstract: Apparatus and methods for variable capacitor arrays are provided herein. In certain configurations, an apparatus includes a variable capacitor array and a bias voltage generation circuit. The variable capacitor array includes a plurality of metal oxide semiconductor (MOS) variable capacitor cells, which include one or more pairs of MOS capacitors implemented in anti-parallel and/or anti-series configurations. In certain implementations, the MOS variable capacitor cells are electrically connected in parallel with one another between a radio frequency (RF) input and an RF output of the variable capacitor array. The bias voltage generation circuit generates bias voltages for biasing the MOS capacitors of the MOS variable capacitor cells.

Abstract: A tunable filter design. The filter is implemented using transmission line sections as inductive and capacitive components. At least one capacitive component is a tunable capacitor. In some implementations, the tunable capacitor may be an interdigitated array of finger elements arranged so that the spacing between fingers may be adjusted. The design has a number of advantages including high capacitance for a given circuit area, small area for a given desired capacitance, mechanical stability, high self resonance frequency, and high quality factor.

Abstract: A highly linear, variable capacitor array constructed from multiple cells. Each cell includes a pair of passive, capacitor components connected in anti-parallel. The capacitor components may be Metal Oxide Semiconductor (MOS) capacitors. A control circuit applies bias voltages to bias voltage terminals associated with each capacitor component, to thereby control the overall capacitance of the array.

Abstract: Mobile phone handsets include a CMOS front end configured for operating across multiple transmit and receive frequencies. The front end typically includes multiple receivers, each covering a different band allocated for cellular service, and requires large, expensive and power-intensive A/D converters and DSPs. Front-end circuits disclosed herein operate with a broadband software-defined radio (SDR), and include a receive Low Noise Amplifier (LNA), transmit Power Amplifier (PA), and an antenna matching network. The front-end provides broadband operation using relatively low power, and minimizes noise in the received signal.

Abstract: In an embodiment, a circuit includes a variable group delay configured to delay a wideband input signal to obtain a delayed input signal; a wideband operational amplifier configured to determine an error signal based on a difference between the delayed input signal and a linearized power amplifier output; a feedback amplifier configured to amplify the error signal to obtain an amplified error signal; and a directional combiner configured to combine the amplified error signal with the power amplifier output to obtain the linearized power amplifier output.

Abstract: In an embodiment, a field programmable analog array (FPAA) comprises state variable filter engines arranged in parallel, each state variable filter engine comprising at least one variable attenuator and at least one variable integrator configured to operate on a wideband analog signal; and a summer configured to add outputs from the state variable filter engines.

Abstract: Embodiments include methods, systems, and apparatuses capable of dynamically and adaptively operating on wideband signals. Examples include state variable filters whose center frequencies can be tuned using variable gain blocks coupled to outputs of filter integrators. First- and second-order state variable filters may operate on signals in parallel and their outputs combined to produce a filtered output. Filters may be tuned to pass or reject signals depending on the application; sample applications include, but are not limited to: agile filtering; spectrum analysis; interference detection and rejection; equalization; direct intermediate-frequency transmission; and single-sideband modulation and demodulation.

Abstract: A signal handler providing high linearity in a small size, applicable across wide operating frequencies and bandwidths, while also adapted to preferred integrated circuit (IC) and printed circuit board technologies. In one implementation, a signal handling apparatus includes an input impedance transformer for receiving an input signal and matching an internal apparatus impedance, a splitter for providing N split signals, a number of signal processing circuits for processing the N split signals, a combiner for combining the N split signals into a combined signal, and output impedance transformer for receiving the combined signal and for matching the internal apparatus impedance to an output impedance of the apparatus. The apparatus may provide filtering, duplexing and other radio frequency signal processing functions. A tunable duplexer may be implemented using a vector inductor and tunable capacitor array with frequency dependent impedance transformers.

Abstract: Apparatus and methods for vector inductors are provided herein. In certain configurations, an apparatus includes a vector inductor comprising a plurality of conductors arranged in a stack and separated from one another by dielectric. The conductors are tightly coupled to one another to provide a relatively high amount of mutual inductance. For example, adjacent conductors in the stack can be mutually coupled with a coupling coefficient k that is at least 0.5, or more particularly, 0.9 or greater. In certain implementations, the conductors are electrically connected in parallel with one another to provide the vector inductor with low resistance. However, tight coupling between the conductors in the stack can result in vector inductor having an overall inductance that is similar to that of a self-inductance of an individual conductor in the stack. The Q-factor of the vector inductor can be increased by the inclusion of additional conductors in the stack.

Abstract: An inductor component includes a plurality of conductive elements, each formed as an individual patch of conductive material, with the conductive elements arranged in a vertical stack and tightly coupled to one another. Dielectric is disposed between more adjacent conductive elements, the dielectric has a permittivity and is sufficiently thin so as to provide a mutual inductance factor of at least one-half or greater between adjacent ones of the conductive elements. The dielectric is typically thinner than the adjacent conductors.

Abstract: Apparatus and methods for variable capacitor arrays are provided herein. In certain configurations, an apparatus includes a variable capacitor array and a bias voltage generation circuit. The variable capacitor array includes a plurality of metal oxide semiconductor (MOS) variable capacitor cells, which include one or more pairs of MOS capacitors implemented in anti-parallel and/or anti-series configurations. In certain implementations, the MOS variable capacitor cells are electrically connected in parallel with one another between a radio frequency (RF) input and an RF output of the variable capacitor array. The bias voltage generation circuit generates bias voltages for biasing the MOS capacitors of the MOS variable capacitor cells.

Abstract: Broadband analog radio-frequency devices can be used to create building blocks for scalable analog signal processors that operate over bandwidths of 50 MHz to 20 GHz or more. Example devices include integrators (transconductors), digitally controlled attenuators, buffers, and scalable summers implemented using deep sub-micron CMOS technology. Because the devices are implemented in CMOS, the ratio of trace/component size to signal wavelength is about the same as that of low-frequency devices implemented in printed circuit boards. Combining this scaling with high gain/high bandwidth enables implementation of feedback and programmability for broadband analog signal processing.

Abstract: Embodiments include methods of tuning state variable filters. Examples include state variable filters whose center frequencies can be tuned using variable gain blocks coupled to outputs of filter integrators. First- and second-order state variable filters may operate on signals in parallel and their outputs combined to produce a filtered output. Filters may be tuned to pass or reject signals depending on the application; sample applications include, but are not limited to: agile filtering; spectrum analysis; interference detection and rejection; equalization; direct intermediate-frequency transmission; and single-sideband modulation and demodulation.

Abstract: A multi-stage signal handling circuit. Operating as a combiner or splitter, first stage transformers match low input impedance at a first set of differential terminals, and second stage transformers match expected higher impedance at second terminal(s). Transformer windings are mirror image, vertically aligned, meandering conductive tracks disposed on opposite sides of a PCB. Air columns above or below the conductive tracks reduce ground plane effects. A capacitor provided across the differential input terminals of each transformer is chosen to further match the power amplifier output, including consideration of inherent inductance presented by the circuit tracks and vias between transformer sections.

Abstract: A biquad wideband signal processing circuit can operate over bandwidths of 50 MHz to 20 GHz or more. The biquad circuit employs a configuration of integrators (transconductors), buffers, and scalable summers that can be implemented using deep sub-micron CMOS technology. Combining this scaling with high gain/high bandwidth enables implementation of feedback and programmability for broadband analog signal processing. A biquad circuit implementing a number of parallel integrator lines having adjustable gain provides greater accuracy, stability, and bandwidth, and allows for control of process variations and temperature variation in real-time.

Abstract: Embodiments provide for dramatically improved interference resistance in advanced communications applications, where the frequency range can exceed 1 GHz. Such embodiments may be implemented using wideband technology to provide a wideband compressive sampling architecture that is capable of superior interference rejection through RF front end cancellation.

Abstract: In an embodiment, a field programmable analog array (FPAA) comprises state variable filter engines arranged in parallel, each state variable filter engine comprising at least one variable attenuator and at least one variable integrator configured to operate on a wideband analog signal; and a summer configured to add outputs from the state variable filter engines.