Abstract: A stress-reduced silicon photonics semiconductor wafer includes a silicon nitride layer on a backside of the wafer. At least one silicon nitride stress-reduction configuration is on a topside of the wafer. At least one silicon nitride photonics device is also on the topside of the wafer. A silicon photonics device can be situated in the wafer.

Abstract: A semiconductor structure includes a substrate having a first dielectric constant, a porous semiconductor layer situated over the substrate, and a crystalline epitaxial layer situated over the porous semiconductor layer. A first semiconductor device is situated in the crystalline epitaxial layer. The porous semiconductor layer has a second dielectric constant that is substantially less than the first dielectric constant such that the porous semiconductor layer reduces signal leakage from the first semiconductor device. The semiconductor structure can include a second semiconductor device situated in the crystalline epitaxial layer, and an electrical isolation region separating the first and second semiconductor devices.

Abstract: A bipolar complementary-metal-oxide-semiconductor (BiCMOS) device includes a MOS transistor including CMOS nickel silicided regions in a CMOS region, and a bipolar transistor in a bipolar region. The bipolar transistor includes a nickel silicided emitter, a collector, and a base including an intrinsic base, a link base, and a nickel silicided extrinsic base. The intrinsic base is situated between the nickel silicided emitter and the collector. A dielectric spacer separates the link base from the nickel silicided emitter. The nickel silicided extrinsic base provides an electrical connection to the link base and the intrinsic base. A nickel silicided collector sinker provides an electrical connection to the collector. The CMOS nickel silicided regions, nickel silicided emitter, nickel silicided extrinsic base, and nickel silicided collector sinker can include an additive of molybdenum (Mo) and/or platinum (Pt). A low temperature rapid thermal anneal can be performed so as to prevent deactivation of dopants.

Abstract: A semiconductor-on-insulator (SOI) device includes a semiconductor layer situated over a buried oxide layer, the buried oxide layer being situated over a substrate. An SOI transistor is situated in the semiconductor layer and includes a transistor body, gate fingers, source regions, and drain regions. The transistor body has a first conductivity type. The source regions and the drain regions have a second conductivity type opposite to the first conductivity type. The transistor body is electrically tied to at least one source region. An asymmetric halo-implant region having the first conductivity type adjoins the at least one source region. No halo-implant region adjoins the drain regions.

Abstract: A method of integrating an optoelectronic device comprising a Pockels material, such as lithium niobate (LiNbO3), includes forming an optoelectronic device layer over a semiconductor layer. The optoelectronic device layer includes a patterned optoelectronic device segment in an interlayer dielectric. A window is etched in the interlayer dielectric using the patterned optoelectronic device segment as a sacrificial etch stop. The patterned optoelectronic device segment is removed in the window. The optoelectronic device comprising the Pockels material is formed in place of the removed patterned optoelectronic device segment. The optoelectronic device comprising the Pockels material may be formed from an optoelectronic chiplet.

Abstract: A bipolar complementary-metal-oxide-semiconductor (BiCMOS) device includes a MOS transistor including CMOS nickel silicided regions in a CMOS region, and a bipolar transistor in a bipolar region. The bipolar transistor includes a nickel silicided emitter, a collector, and a base including an intrinsic base, a link base, and a nickel silicided extrinsic base. The intrinsic base is situated between the nickel silicided emitter and the collector. A dielectric spacer separates the link base from the nickel silicided emitter. The nickel silicided extrinsic base provides an electrical connection to the link base and the intrinsic base. A nickel silicided collector sinker provides an electrical connection to the collector. The CMOS nickel silicided regions, nickel silicided emitter, nickel silicided extrinsic base, and nickel silicided collector sinker can include an additive of molybdenum (Mo) and/or platinum (Pt). A low temperature rapid thermal anneal can be performed so as to prevent deactivation of dopants.

Abstract: A semiconductor structure includes a group IV substrate and a patterned group III-V device over the group IV substrate. Precursor stacks having at least one precursor metal are situated over at least one portion of the patterned group III-V device. A blanket dielectric layer is situated over the patterned group III-V device. Contact holes in the blanket dielectric layer are situated over each precursor stack. A filler metal is situated in each contact hole and over each precursor stack. The patterned group III-V device can be optically and/or electrically connected to group IV devices in the group IV substrate. Additional contact holes in the blanket dielectric layer can be situated over the group IV devices and filled with the filler metals.

Abstract: A semiconductor structure includes a group IV substrate and a patterned group III-V device over the group IV substrate. A blanket dielectric layer is situated over the patterned group III-V device. Contact holes in the blanket dielectric layer are situated over the patterned group III-V device. A liner stack having at least one metal liner is situated in each contact hole. Filler metals are situated over each liner stack and fill the contact holes. The patterned group III-V device can be optically and/or electrically connected to group IV devices in the group IV substrate.

Abstract: A field effect transistor (FET) includes an active region including a source region, a drain region, and a channel region. The channel region is under a gate and situated between the source region and the drain region. A field region is next to the active region. The channel region has an interface with the field region. The gate has a wide outer gate segment proximate to the interface and a narrow inner gate segment distant from the interface. The wide outer gate segment produces an outer channel length greater than an inner channel length that is produced from the narrow inner gate segment, thereby reducing a leakage current of the FET during an OFF state.

Abstract: A semiconductor structure includes a group IV substrate including group IV dies separated by a scribe line. A group IIIV-chiplet is situated over the group IV substrate at least partially over the scribe line. A group III-V process control monitoring device in the group III-V chiplet is situated over the scribe line. Functional group III-V optoelectronic devices can be situated over the group IV dies.

Abstract: A germanium-on-silicon photodetector is fabricated by forming a thin silicon oxide layer on a silicon layer, and then forming a silicon nitride layer on the silicon oxide layer. A nitride dry etch process is used to etch an opening through the silicon nitride layer (through a photoresist mask). The nitride dry etch is stopped on the thin silicon oxide layer, preventing damage to the underlying silicon layer. A wet etch is then performed through the opening in the silicon nitride layer to remove the exposed silicon oxide layer. The wet etch exposes (and cleans) a portion of the underlying silicon layer. High-quality germanium is epitaxially grown over the exposed portion of the silicon layer, thereby providing a germanium structure that forms the intrinsic region of a PIN photodiode.

Abstract: A radio frequency (RF) device includes a phase-change material (PCM) situated over a sheet of thermally conductive and electrically insulating material, a heating element situated under the sheet of thermally conductive and electrically insulating material, and an input/output terminal situated over the PCM. The heating element is situated in a dielectric. A heat spreader is situated under the dielectric and over a substrate. Metal interconnect layers can be situated under and/or over the PCM, with the substrate situated below the metal interconnect layers.

Abstract: A semiconductor-on-insulator (SOI) transistor includes a semiconductor layer situated over a buried oxide layer, the buried oxide layer being situated over a substrate. The SOI transistor is situated in the semiconductor layer and includes a transistor body, gate fingers, source regions, and drain regions. The transistor body has a first conductivity type. The source regions and the drain regions have a second conductivity type opposite to the first conductivity type. A heavily-doped body-implant region has the first conductivity type and overlaps at least one source region. A common silicided region electrically ties the heavily-doped body-implant region to the at least one source region. The common silicided region can include a source silicided region, and a body tie silicided region situated over the heavily-doped body-implant region. The source silicided region can be separated from a drain silicided region by the gate fingers.

Abstract: A semiconductor structure includes a group IV substrate and a patterned group III-V device over the group IV substrate. Precursor stacks having at least one precursor metal are situated over at least one portion of the patterned group III-V device. A blanket dielectric layer is situated over the patterned group III-V device. Contact holes in the blanket dielectric layer are situated over each precursor stack. A filler metal is situated in each contact hole and over each precursor stack. The patterned group III-V device can be optically and/or electrically connected to group IV devices in the group IV substrate. Additional contact holes in the blanket dielectric layer can be situated over the group IV devices and filled with the filler metals.

Abstract: A semiconductor-on-insulator (SOI) transistor includes a semiconductor layer situated over a buried oxide layer, the buried oxide layer being situated over a substrate. The SOI transistor is situated in the semiconductor layer and includes a transistor body, gate fingers, source regions, and drain regions. The transistor body has a first conductivity type. The source regions and the drain regions have a second conductivity type opposite to the first conductivity type. A heavily-doped body-implant region has the first conductivity type and overlaps at least one source region. A common silicided region electrically ties the heavily-doped body-implant region to the at least one source region. The common silicided region can include a source silicided region, and a body tie silicided region situated over the heavily-doped body-implant region. The source silicided region can be separated from a drain silicided region by the gate fingers.

Abstract: A semiconductor structure includes a group IV substrate and a patterned group III-V device over the group IV substrate. A blanket dielectric layer is situated over the patterned group III-V device. Contact holes in the blanket dielectric layer are situated over the patterned group III-V device. A liner stack having at least one metal liner is situated in each contact hole. Filler metals are situated over each liner stack and fill the contact holes. The patterned group III-V device can be optically and/or electrically connected to group IV devices in the group IV substrate.

Abstract: A semiconductor structure includes a group IV substrate and a patterned group III-V device over the group IV substrate. A blanket dielectric layer is situated over the patterned group III-V device. A contact metal is situated within the blanket dielectric layer and an interconnect metal is situated over the blanket dielectric layer. The blanket dielectric layer can be substantially planar. The contact metal and the interconnect metal can be electrically connected to the patterned group III-V device. The patterned group III-V device can be optically and/or electrically connected to group IV devices in the group IV substrate.

Abstract: A semiconductor structure includes a group III-V chiplet over a group IV substrate. A group IV optoelectronic device is situated in the group IV substrate. A patterned group III-V optoelectronic device is situated in the group III-V chiplet. A heating element is near the group IV optoelectronic device, or alternatively, near the patterned group III-V optoelectronic device. A dielectric layer is over the patterned group III-V optoelectronic device. A venting hole is in the dielectric layer in proximity of the heating element. A cavity is in the group IV substrate in proximity to the heating element.

Abstract: A bipolar complementary-metal-oxide-semiconductor (BiCMOS) device includes a MOS transistor including CMOS nickel silicided regions in a CMOS region, and a bipolar transistor in a bipolar region. The bipolar transistor includes a nickel silicided emitter, a collector, and a base including an intrinsic base, a link base, and a nickel silicided extrinsic base. The intrinsic base is situated between the nickel silicided emitter and the collector. A dielectric spacer separates the link base from the nickel silicided emitter. The nickel silicided extrinsic base provides an electrical connection to the link base and the intrinsic base. A nickel silicided collector sinker provides an electrical connection to the collector. The CMOS nickel silicided regions, nickel silicided emitter, nickel silicided extrinsic base, and nickel silicided collector sinker can include an additive of molybdenum (Mo) and/or platinum (Pt). A low temperature rapid thermal anneal can be performed so as to prevent deactivation of dopants.

Abstract: In fabricating a semiconductor structure, a group IV substrate and a group III-V chiplet are provided. The group III-V chiplet is bonded to the group IV substrate, and patterned to produce a patterned group III-V device. A blanket dielectric layer is formed over the patterned group III-V device. A first contact hole is formed in the blanket dielectric layer over a first portion of the patterned group III-V device. A first liner stack and a first filler metal are subsequently formed in the first contact hole. A second contact hole is formed in the blanket dielectric layer over a second portion of the patterned group III-V device. A second liner stack and a second filler metal are subsequently formed in the second contact hole. A first bottom metal liner of the first liner stack can be different from a second bottom metal liner of the second liner stack.