Abstract: A new data packet cell control method and apparatus, particularly, though not exclusively, for use with I/O packet cell source and destination resource networks using shared central multi-port internally cached dynamic random access memory (AMPIC DRAM), wherein a separate control path architecture is used, also incorporating AMPIC DRAM technology, to obviate problems with data traffic congestion resulting from significant I/O resource and for bandwidth requirement increases, and doing so while enabling scaling with data path, and retaining quality of service and increased multicast functionality, as well.

Abstract: A technique for encoding (and decoding) escape and other characters in data packets at high rates of speed in HDLC and similar data processing through the use of groups of FIFO data streams parallely fed to and from a multilane highway matrix of input data and escape character switched busses and at relatively low clocking speeds, while running multiple byte streams at a time.

Abstract: A novel chip layout for a network wherein pluralities of I/O data ports are each connected to transmit/receive SRAM buffer banks operable under arbitration units to access pluralities of internally cached DRAM banks via internal busses to enable switching data connections amongst all data ports through the appropriate buffers, the chip layout having, data ports substantially symmetrically placed with each data port connected to each arbitration unit and each transmit/receive buffer bank, and with each data port enabled to write into any DRAM bank, with the connections being effected such that each data port is substantially symmetric with respect to DRAM bank, arbitration unit and transmit/receive buffer banks and busses; and with timing clocks centrally placed on the chip to minimize clock skew by symmetric clock distribution.

Abstract: An electronic circuit board assembly and method that enable close stacking and cooling of closely positioned pluralities of similar electronic I/O or memory boards and requiring high speed communication between the boards, such as high speed switching amongst the I/O terminals of the boards or CPU processing, and having an upper and a lower set of similar spaced groups of closely spaced vertical boards; powering terminals aligned along the upper edges of the upper set of boards, and along the lower edges of the lower set of boards, and terminals for connection with a switching fabric disposed along the lower edges of the upper set of boards and the upper edges of the lower set of boards; power backing planes mounted to power and support the lateral edges of the respective sets of groups of boards and extending across the upper and lower sections of the frame; and a plurality of parallel closely spaced vertical switching fabric boards comprising switching fabric (or CPU processing boards) and centrally mounted