Abstract: The present disclosure provides a method for making a shallow trench structure, which at least includes the following: preparing a substrate; forming a first material layer on one side of the substrate; forming a second material layer on the first material layer; forming a shallow trench in the second material layer, the first material layer and the substrate; performing a first lateral etching on the second material layer from the shallow trench to both sides by using wet etching; performing a second lateral etching on the first material layer from the shallow trench to both sides by using dry etching. The present disclosure solves the problem of the damage to the silicon in the shallow trench caused by the traditional lateral etching technology.

Abstract: The present disclosure provides a method and system for manufacturing a semiconductor layer. The method includes: placing a first wafer in a cavity to form a metal film on the first wafer; before forming the metal film, the temperature inside the cavity is a first temperature; transferring the first wafer on which the metal film has been formed out of the cavity; the temperature in the cavity is a second temperature, and the second temperature is greater than the first temperature; introducing an inert gas into the cavity to cool the cavity, such that the temperature in the cavity is equal to the first temperature; after the temperature in the cavity is equal to the first temperature, placing a second wafer in the cavity to form the metal film on the second wafer. The manufacturing method can reduce the defects on the surface of the metal film.

Abstract: A semiconductor device and a manufacturing method is provided. The semiconductor device includes a substrate, a shallow trench isolation structure, a dielectric layer, a gate, a source and a drain. The substrate includes a first region and a second region. The shallow trench isolation structure is arranged on the first region and the second region, and the shallow trench isolation structure is lower than a surface of the substrate and forms an opening. The dielectric layer is arranged in the opening and on the substrate, and a height of the dielectric layer in the second region is greater than that in the first region. The gate is arranged on the dielectric layer. The source is arranged on the substrate and located on a side of the gate. The drain is arranged on the substrate and located on the other side of the gate.

Abstract: The present disclosure provides a method for making a shallow trench structure, which at least includes the following: preparing a substrate; forming a first material layer on one side of the substrate; forming a second material layer on the first material layer; forming a shallow trench in the second material layer, the first material layer and the substrate; performing a first lateral etching on the second material layer from the shallow trench to both sides by using wet etching; performing a second lateral etching on the first material layer from the shallow trench to both sides by using dry etching. The present disclosure solves the problem of the damage to the silicon in the shallow trench caused by the traditional lateral etching technology.

Abstract: The present disclosure discloses an overlay mark, an overlay marking method and an overlay measuring method. The overlay marking method includes at least: preparing a first material layer; preparing a first mark group on the first material layer, and the first mark group is a centrally symmetrical pattern; preparing a second material layer on the first material layer; preparing a second mark group corresponding to the first mark group on the second material layer, and the second mark group is a centrally symmetrical pattern; centers of symmetry of the second mark group and the first mark group are located on the same vertical line; preparing a third material layer on the second material layer; preparing a third mark group corresponding to the first mark group and the second mark group on the third material layer, and the third mark group is a centrally symmetrical pattern.

Abstract: The present disclosure provides a method and system for manufacturing a semiconductor layer. The method includes: placing a first wafer in a cavity to form a metal film on the first wafer; before forming the metal film, the temperature inside the cavity is a first temperature; transferring the first wafer on which the metal film has been formed out of the cavity; the temperature in the cavity is a second temperature, and the second temperature is greater than the first temperature; introducing an inert gas into the cavity to cool the cavity, such that the temperature in the cavity is equal to the first temperature; after the temperature in the cavity is equal to the first temperature, placing a second wafer in the cavity to form the metal film on the second wafer. The manufacturing method can reduce the defects on the surface of the metal film.

Abstract: A semiconductor structure and method for forming such a structure are disclosed by the present invention. In the method, before a first trench in a pre-processed substrate is filled with any filling material, an auxiliary layer is formed over an inner surface of the first trench. Afterward, a first filling dielectric is formed and an etch back process is performed so that a top surface of the first filling dielectric is higher than that of the pre-processed substrate, and a second filling dielectric is then formed and subject to a second planarization process.

Abstract: A diffused field-effect transistor (FET) and a method of fabricating same are disclosed. The diffused FET is dually optimized in voltage resistance by incorporating both a trench isolation structure and a thick second oxide layer and thus has a more significantly improved breakdown voltage. With the thick second oxide layer ensuring suitable voltage resistance of the transistor device, its on-resistance can be reduced either by reducing the size of the trench isolation structure or increasing an ion dopant concentration of a drift region. As such, a good tradeoff between voltage resistance and on-resistance is achievable.

Abstract: A method for fabricating MOSFET is disclosed. In the method, after a gate is formed by etching a deposited undoped or lightly-doped polysilicon layer, with the portions of the gate above channel edge between a channel region and STI region being protected, ions are doped into the remaining gate portion during source/drain implantation. As a result, each of the gate portions above channel edge is constructed of a doped second polysilicon layer stacked with undoped (or lightly-doped) first polysilicon layers, while the remaining gate portion is simply constituted by the doped second polysilicon layer. This can increase a threshold voltage of the MOSFET at channel edge. Optionally, before the gate is formed by etching the polysilicon, the portions of the polysilicon above the channel edge may be protected, followed by doping ions into the remaining portions of the polysilicon.

Abstract: A current source includes a substrate, a base region of a first doping type formed in the substrate, an emitter region of a second doping type formed in the substrate and surrounding the base region, a first collector region of the second doping type formed in the base region, and at least one second collector region of the second doping type formed in the base region, wherein the emitter region includes a deep-well portion and an extending portion, the deep-well portion situated beneath the base region, the extending portion laterally surrounding the base region, the extending portion joined at its bottom to the deep-well portion, the extending portion being flush at its top with a top surface of the substrate. A method of forming the current source is also disclosed.

Abstract: A method for forming a semiconductor structure is disclosed. Among a stack of mask layers, any other layers above the lowermost thin film layer are subsequently removed to expose the lowermost thin film layer and then the lowermost thin film layer is separately removed by a dry etching process. This improves an etching uniformity of the lowermost thin film layer and ameliorates the issue of material residues. Moreover, thanks to the anisotropic characteristic of the dry etching process, lateral etching of side walls of a trench isolation structure can be mitigated.

Abstract: A pre-processing method, a method for forming a metal silicide and a semiconductor processing apparatus are disclosed by the present invention. In the pre-processing method, a plasma etching process is performed on a semiconductor structure including a substrate. A first conductive portion and an isolation spacer covering a side surface of the first conductive portion are formed on a surface of an active area in the substrate. In the plasma etching process, a bias voltage applied to a surface of the semiconductor structure is adjusted by adjusting power outputs of two RF sources and is not lower than 150 V. In the metal silicide formation method, after a semiconductor structure including a first conductive portion and a second conductive portion is pre-processed in the manner as described above, a metal film is deposited thereon and annealed to result in the formation of the metal silicide.

Abstract: A silicon island structure and a method of fabricating same are disclosed. The method includes: forming multiple first trenches in a silicon substrate; forming second trenches by partially filling some of the first trenches with an insulating material; depositing a protective layer over the silicon substrate and over the second trenches; removing the protective layer over bottoms of the second trenches and the insulating material under the second trenches, thereby exposing sidewalls of some first trenches; oxidizing portions of the silicon substrate between the exposed sidewalls of the first trenches to form an oxide layer; removing the protective layer covering sidewalls of the second trenches; and filling the second trenches with an isolating material to form isolations, wherein portions of the silicon substrate between the isolations define silicon islands. This method enables the formation of silicon islands at desired locations with reduced process complexity and cost.

Abstract: A method for forming a metal silicide layer, a semiconductor device and a method for fabricating the device are disclosed. Through depositing a buffer layer between a metal layer and a substrate, metal atoms in the metal layer will diffuse, during a thermal annealing process, through the buffer layer into the substrate while being buffered by the buffer layer. As a result, the diffusion speed and depth of the metal atoms in the substrate are both reduced, and a reaction between the metal and silicon in the substrate is hence slowed down. In this way, the risk of agglomeration of the resulting metal silicide can be effectively lowered, avoiding pinhole defects occurring in the substrate and improving the interface roughness of the resulting metal silicide layer.