Abstract: A technique for high speed transmission of digital signals on a bus line with reduced signal ringing, bounce and bus contention current. The approach uses a multi-partitioned driver design with temporary and steady state parts incorporating internal feedback and delay techniques to control the output slew rate. A built-in function outputs the driving status of the transceiver and allows the output to enter the high impedance status asynchronously.

Abstract: A bus system wherein N-bit devices (12b,12c) attached to the lower half (30L) of a 2N-bit bus (30) communciate with 2N-bit (12a, 12d) devices attached to the full bus. Bi-directional registered transceivers (60,62,65,67) are coupled between the upper and lower halves of the bus. The N-bit devices are capable of asserting a pair of signals called HOLDN and LATCHN. For a 2 N-bit source device transmitting data to an N-bit sink device, the 2 N-bit source puts 2 N bits of data on the upper and lower halves of the bus during a given cycle, during which the N-bit sink device samples the N bits on the lower half of the bus. The assertion of HOLDN causes the N bits on the upper half of the bus to be latched and subsequently driven onto the lower half of the bus. Where an N-bit source device is communicating to a 2 N-bit sink device, the N-bit device puts the high order N bits and low order N bits of data on the lower half of the bus on successive cycles.

Abstract: A dual-bus architecture that includes a high-seed system bus, called the NexBus (20), and a slower peripheral bus, called the alternate bus or AB (25). The NexBus and AB are coupled by control logic (45) which includes an arbiter (50) and an alternate bus interface (ABI) (60). The ABI is treated as a master for both the NexBus and the AB. While it would be possible to have the adapter always request the AB (which also requires the NexBus), that would slow down NexBus operations to the bandwidth of the AB. This problem is avoided by providing two request lines for each adapter, -NREQ (NexBus only) and -AREQ (both buses), having the adapter normally assert -NREQ first. However, if the addressed device is on the AB, the ABI automatically detects this fact and attempts to do a crossing transfer to the AB, even though the request was for the NexBus only.

Abstract: An improved branch prediction cache (BPC) scheme that utilizes a hybrid cache structure. The BPC provides two levels of branch information caching. The fully associative first level BPC is a shallow but wide structure (36 32-byte entries), which caches full prediction information for a limited number of branch instructions. The second direct mapped level BPC is a deep but narrow structure (256 2-byte entries), which caches only partial prediction information, but does so for a much larger number of branch instructions. As each branch instruction is fetched and decoded, its address is used to perform parallel look-ups in the two branch prediction caches.

Abstract: A system which integrates the multiple instruction queues and the branch target cache (BTC) of a high performance CPU design into a single physical structure. Effectively, the queues are merged into the BTC in such a manner that, at any point in time, most of this structure functions as a BTC while certain entries function as instruction queues.By using parts of the BTC to serve as instruction queues, the inefficiency of separate queue structures is eliminated and the queues are implemented with the greater device density characteristic of the RAM structure which the BTC core is based on. This merging of these structures also substantially simplifies the instruction queue control and the routing of instruction words between BTC entries and queues.

Abstract: The present invention provides for the updating of both the instructions in a branch prediction cache and instructions recently provided to an instruction pipeline from the cache when an instruction being executed attempts to change such instructions ("Store-Into-Instruction-Stream"). The branch prediction cache (BPC) includes a tag identifying the address of instructions causing a branch, a record of the target address which was branched to on the last occurrence of each branch instruction, and a copy of the first several instructions beginning at this target address. A separate instruction cache is provided for normal execution of instructions, and all of the instructions written into the branch prediction cache from the system bus must also be stored in the instruction cache. The instruction cache monitors the system bus for attempts to write to the address of an instruction contained in the instruction cache.

Abstract: A pipeline control system is distributed over the functional units (15, 17, 20, 25) in a processor (10). Decoder logic (12) issues operations, each with an associated tag, to the functional units, with up to n operations allowed to be outstanding. The units execute the operations and report termination information back to the decoder logic, but do not irrevocably change the state of the machine. Based on the termination information, the decoder logic retires normally terminated operations in order. If an operation terminates abnormally, the decoder logic instructs the units to back out of those operations that include and are later than the operation that terminated abnormally.

Abstract: An improved branch prediction cache (BPC) scheme that utilizes a hybrid cache structure. The BPC provides two levels of branch information caching. The fully associative first level BPC is a shallow but wide structure (36 32-byte entries), which caches full prediction information for a limited number of branch instructions. The second direct mapped level BPC is a deep but narrow structure (256 2-byte entries), which caches only partial prediction information, but does so for a much larger number of branch instructions. As each branch instruction is fetched and decoded, its address is used to perform parallel look-ups in the two branch prediction caches.

Abstract: A technique that efficiently allocates the servicing of interrupts among a plurality of CPUs in a multiprocessor computer system requires no change in software that was written for a system with one CPU and one PIC. Symmetric and asymmetric configurations contemplate a primary CPU (15a) and one or more secondary CPU's (15b-d) responding to and servicing multiple sets of interrupts. Both configurations include interrupt supervisory logic to support such operation. The symmetric configuration provides a PIC (20a-d) for each CPU in the system. All the PICs are located at the same I/O address, and separate provision is made to specify which PIC is to respond to an interrupt acknowledge cycle initiated by a particular CPU. The asymmetric configuration of the present invention provides PIC (20a) for the primary CPU (15a) only. That PIC's interrupt line is communicated only to the primary CPU. Another mechanism, such as an ATTN facility (95), is provided to drive the secondary CPU's interrupt inputs.

Abstract: The present invention provides an improved branch prediction cache (BPC) structure that combines various separate structures into one integrated structure. In conjunction with doing this, the present invention is able to share significant portions of hardware cost and design complexity overhead. As a result, the cost-performance trade-off for implementing dynamic branch prediction for target address, branch direction, and target instructions aspects of branches shifts to where "full" branch prediction is now more practical.