Patents Assigned to Nexgen Power Systems, Inc.
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Publication number: 20240120417Abstract: A gallium nitride (GaN) power device includes a GaN substrate structure having a first surface and a second surface, a metallic layer coupled to the second surface of the GaN substrate structure, and an active region including an array of vertical fin-based field effect transistors (FinFETs) coupled to the GaN substrate structure. The GaN power device also includes an edge termination structure circumscribing the active region and a seal ring structure circumscribing the edge termination structure and comprising a seal ring metal pad operable to conduct charge from the edge termination structure to the metallic layer.Type: ApplicationFiled: April 20, 2023Publication date: April 11, 2024Applicant: Nexgen Power Systems, Inc.Inventors: Kyoung Wook Seok, Clifford Drowley, Andrew J. Walker, Andrew P. Edwards
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Patent number: 11948801Abstract: A method of manufacturing a vertical FET device includes providing a semiconductor substrate structure including a marker layer; forming a hardmask layer coupled to the semiconductor substrate structure, wherein the hardmask layer comprises a set of openings operable to expose an upper surface portion of the semiconductor substrate structure; etching the upper surface portion of the semiconductor substrate structure to form a plurality of fins; etching at least a portion of the marker layer; detecting the etching of the at least a portion of the marker layer; epitaxially growing a semiconductor layer in recess regions disposed between adjacent fins of the plurality of fins; forming a source metal layer on each of the plurality of fins; and forming a gate metal layer coupled to the semiconductor layer.Type: GrantFiled: June 23, 2021Date of Patent: April 2, 2024Assignee: Nexgen Power Systems, Inc.Inventors: Wayne Chen, Andrew P. Edwards, Clifford Drowley, Subhash Srinivas Pidaparthi
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Patent number: 11935838Abstract: A method of forming alignment marks includes providing a III-V compound substrate having a device region and an alignment mark region, forming a hardmask layer having a first set of openings on the alignment mark region exposing a first surface portion of the III-V compound substrate and a second set of openings on the device region exposing a second surface portion of the III-V compound substrate, etching the exposed surface of the III-V compound substrate using the hardmask layer as a mask to form a plurality of trenches, and epitaxially regrowing a semiconductor layer in the trenches to form the alignment marks extending to a predetermined height over the processing surface of the III-V compound substrate.Type: GrantFiled: March 29, 2022Date of Patent: March 19, 2024Assignee: Nexgen Power Systems, Inc.Inventors: Clifford Drowley, Ray Milano, Robert Routh, Subhash Srinivas Pidaparthi, Andrew P. Edwards
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Patent number: 11929440Abstract: Methods and semiconductor devices are provided. A vertical junction field effect transistor (JFET) includes a substrate, an active region having a plurality of semiconductor fins, a source metal layer on an upper surface of the fins, a source metal pad layer coupled to the semiconductor fins through the source metal layer, a gate region surrounding the semiconductor fins, and a body diode surrounding the gate region.Type: GrantFiled: March 9, 2023Date of Patent: March 12, 2024Assignee: Nexgen Power Systems, Inc.Inventors: Clifford Drowley, Andrew P. Edwards, Subhash Srinivas Pidaparthi, Ray Milano
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Publication number: 20240039411Abstract: A method of setting a synchronous rectifier on-time value includes determining that a time interval has occurred, receiving a number of triangular current mode (TCM) pulses measured during the time interval, and determining a pulse comparison value equal to a number of switching period pulses during the time interval minus the number of TCM pulses during the time interval. The method also includes increasing the synchronous rectifier on-time if the pulse comparison value is greater than or equal to a threshold and decreasing the synchronous rectifier on-time if the pulse comparison value is less than the threshold.Type: ApplicationFiled: August 11, 2023Publication date: February 1, 2024Applicant: Nexgen Power Systems, Inc.Inventor: Anders Lind
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Publication number: 20230411525Abstract: A method of fabricating a vertical fin-based field effect transistor (FET) includes providing a semiconductor substrate having a first surface and a second surface, the semiconductor substrate having a first conductivity type, epitaxially growing a first semiconductor layer on the first surface of the semiconductor substrate, the first semiconductor layer having the first conductivity type and including a drift layer and a graded doping layer on the drift layer, and epitaxially growing a second semiconductor layer having the first conductivity type on the graded doping layer. The method also includes forming a metal compound layer on the second semiconductor layer, forming a patterned hard mask layer on the metal compound layer, and etching the metal compound layer and the second semiconductor layer using the patterned hard mask layer as a mask exposing a surface of the graded doping layer to form a plurality of fins surrounded by a trench.Type: ApplicationFiled: June 23, 2023Publication date: December 21, 2023Applicant: Nexgen Power Systems, Inc.Inventors: Clifford Drowley, Ray Milano, Subhash Srinivas Pidaparthi, Andrew P. Edwards, Hao Cui, Shahin Sharifzadeh
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Patent number: 11837951Abstract: A self-oscillating converter includes a power transistor coupled to a primary winding for controlling current flow in the primary winding, and a turn-on circuit configured to turn on the power transistor for maintaining oscillation in the self-oscillating converter. The self-oscillating converter also includes a turn-off circuit configured to turn off the power transistor to maintain an on-time of the power transistor at a pre-set value for power factor correction, and modulate the on-time of the power transistor to regulate the output current in the load device.Type: GrantFiled: October 11, 2021Date of Patent: December 5, 2023Assignee: Nexgen Power Systems, Inc.Inventor: Charles Coles
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Publication number: 20230378750Abstract: A method of clamping a voltage includes providing a fin-based field effect transistor (FinFET) device. The FinFET device includes an array of FinFETs. Each FinFET includes a source contact electrically coupled to a fin and a gate contact. The method also includes applying the voltage to the source contact and applying a second voltage to the gate contact. The voltage is greater than the second voltage. The method further includes increasing the voltage to a threshold voltage and conducting current from the source contact to the gate contact in response to the voltage reaching the threshold voltage.Type: ApplicationFiled: April 20, 2023Publication date: November 23, 2023Applicant: Nexgen Power Systems, Inc.Inventors: Andrew J. Walker, Clifford Drowley, Subhash Srinivas Pidaparthi, Andrew P. Edwards, Shahin Sharifzadeh, Joseph Tandingan
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Publication number: 20230378348Abstract: A vertical, FinFET device includes an array of FinFETs comprising a plurality of rows and columns of fins. Each of the fins has a fin length and a fin width, a first fin tip, a second fin tip, and a central region disposed between the first fin tip of a first row of the plurality of rows and the second fin tip of a second row of the plurality of rows. The central region is characterized by an electrical conductivity. The FinFET device also includes a neutralized region including the first fin tip, a region between the first row of the plurality of rows and the second row of the plurality of rows, and the second fin tip. The neutralized region is characterized by a second electrical conductivity less than the electrical conductivity of the central region. The FinFET device further includes an electrical conductor disposed over the neutralized region.Type: ApplicationFiled: April 20, 2023Publication date: November 23, 2023Applicant: Nexgen Power Systems, Inc.Inventors: Clifford Drowley, Andrew J. Walker, Andrew P. Edwards, Subhash Srinivas Pidaparthi, Thomas E. Kopley
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Patent number: 11824430Abstract: A method of measuring an AC input voltage at an input of a power converter includes measuring a DC bus voltage corresponding to the power converter. During a positive half-cycle of the AC input voltage, the method includes measuring a first voltage at the input of the power converter. During a negative half-cycle of the AC input voltage, the method includes turning on a high-side switch, measuring a second voltage at the input of the power converter, and computing a third voltage equal to the second voltage minus the DC bus voltage. The method further includes providing the AC input voltage as the first voltage during the positive AC half-cycle and the third voltage during the negative AC half-cycle.Type: GrantFiled: November 11, 2021Date of Patent: November 21, 2023Assignee: Nexgen Power Systems, Inc.Inventor: Anders Lind
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Publication number: 20230361126Abstract: A vertical fin-based field effect transistor (FinFET) device includes an array of FinFETs comprising a plurality of rows and columns of fins, each of the fins having a fin length and a fin width measured laterally with respect to the fin length and including a first fin tip disposed at a first end of the fin; a second fin tip disposed at a second end of the fin opposing the first end; a bridging structure connecting the first fin tip to an adjacent fin; a central region disposed between the first fin tip and the second fin tip and characterized by an electrical conductivity; and a source contact electrically coupled to the central region. The FinFET device also includes a gate region surrounding the fins.Type: ApplicationFiled: April 20, 2023Publication date: November 9, 2023Applicant: Nexgen Power Systems, Inc.Inventors: Andrew P. Edwards, Andrew J. Walker, Clifford Drowley, Subhash Srinivas Pidaparthi
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Patent number: 11770075Abstract: A method of setting a synchronous rectifier on-time value includes determining that a time interval has occurred, receiving a number of triangular current mode (TCM) pulses measured during the time interval, and determining a pulse comparison value equal to a number of switching period pulses during the time interval minus the number of TCM pulses during the time interval. The method also includes increasing the synchronous rectifier on-time if the pulse comparison value is greater than or equal to a threshold and decreasing the synchronous rectifier on-time if the pulse comparison value is less than the threshold.Type: GrantFiled: November 11, 2021Date of Patent: September 26, 2023Assignee: Nexgen Power Systems, Inc.Inventor: Anders Lind
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Patent number: 11735671Abstract: A method of fabricating a vertical fin-based field effect transistor (FET) includes providing a semiconductor substrate having a first surface and a second surface, the semiconductor substrate having a first conductivity type, epitaxially growing a first semiconductor layer on the first surface of the semiconductor substrate, the first semiconductor layer having the first conductivity type and including a drift layer and a graded doping layer on the drift layer, and epitaxially growing a second semiconductor layer having the first conductivity type on the graded doping layer. The method also includes forming a metal compound layer on the second semiconductor layer, forming a patterned hard mask layer on the metal compound layer, and etching the metal compound layer and the second semiconductor layer using the patterned hard mask layer as a mask exposing a surface of the graded doping layer to form a plurality of fins surrounded by a trench.Type: GrantFiled: April 12, 2022Date of Patent: August 22, 2023Assignee: Nexgen Power Systems, Inc.Inventors: Clifford Drowley, Ray Milano, Subhash Srinivas Pidaparthi, Andrew P. Edwards, Hao Cui, Shahin Sharifzadeh
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Publication number: 20230260996Abstract: A vertical fin-based field effect transistor (FinFET) includes an array of FinFETs comprising a plurality of rows and columns of active fins with source contacts and one or more rows of first inactive fins disposed on a first set of sides of the array of FinFETs. The vertical FinFET also includes one or more columns of second inactive fins disposed on a second set of sides of the array of FinFETs. The first inactive fins and the second inactive fins are characterized by a reduced electrical conductivity compared to an electrical conductivity of the active fins of the array of FinFETs. The vertical FinFET further includes an active gate region surrounding the FinFETs of the array of FinFETs and an additional gate region surrounding the first inactive fins and the second inactive fins. At least a portion of the additional gate region is a neutralized gate region.Type: ApplicationFiled: February 10, 2023Publication date: August 17, 2023Applicant: Nexgen Power Systems, Inc.Inventors: Clifford Drowley, Andrew J. Walker, Andrew P. Edwards, Subhash Srinivas Pidaparthi
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Patent number: 11728415Abstract: A method of forming an alignment contact includes: providing a III-nitride substrate; epitaxially growing a first III-nitride layer on the III-nitride substrate, wherein the first III-nitride layer is characterized by a first conductivity type; forming a plurality of III-nitride fins on the first III-nitride layer, wherein each the plurality of III-nitride fins is separated by one of a plurality of first recess regions, wherein the plurality of III-nitride fins are characterized by the first conductivity type; epitaxially regrowing a III-nitride source contact portion on each of the plurality of III-nitride fins; and forming a source contact structure on the III-nitride source contact portions.Type: GrantFiled: March 24, 2021Date of Patent: August 15, 2023Assignee: Nexgen Power Systems, Inc.Inventors: Clifford Drowley, Andrew P. Edwards, Subhash Srinivas Pidaparthi, Shahin Sharifzadeh
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Publication number: 20230246027Abstract: A vertical fin-based field effect transistor (FinFET) device includes an array of FinFETs comprising a plurality of rows and columns of separated fins. Each of the separated fins has a length and a width measured laterally with respect to the length and includes a first fin tip disposed at a first end of the separated fin, a second fin tip disposed at a second end of the separated fin opposing the first end, a central region disposed between the first fin tip and the second fin tip and characterized by a first electrical conductivity, and a source contact electrically coupled to the central region. The first fin tip and the second fin tip are characterized by a second electrical conductivity less than the first electrical conductivity. The FinFET further includes a first gate region surrounding the first fin tip and a second gate region surrounding the second fin tip.Type: ApplicationFiled: January 17, 2023Publication date: August 3, 2023Applicant: Nexgen Power Systems, Inc.Inventors: Subhash Srinivas Pidaparthi, Clifford Drowley, Shahin Sharifzadeh, Andrew P. Edwards, Andrew Walker, Francis Chai
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Publication number: 20230215958Abstract: Methods and semiconductor devices are provided. A vertical junction field effect transistor (JFET) includes a substrate, an active region having a plurality of semiconductor fins, a source metal layer on an upper surface of the fins, a source metal pad layer coupled to the semiconductor fins through the source metal layer, a gate region surrounding the semiconductor fins, and a body diode surrounding the gate region.Type: ApplicationFiled: March 9, 2023Publication date: July 6, 2023Applicant: Nexgen Power Systems, Inc.Inventors: Clifford Drowley, Andrew P. Edwards, Subhash Srinivas Pidaparthi, Ray Milano
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Publication number: 20220328688Abstract: A III-N-based vertical transistor includes a III-N substrate, a source, a drain, and a channel comprising a III-N crystal material and extending between the source and the drain. The channel includes at least one sidewall surface aligned ±0.3° with respect to an m-plane of the III-N crystal material. The III-N-based vertical transistor also includes a gate electrically coupled to the at least one sidewall surface of the channel.Type: ApplicationFiled: March 29, 2022Publication date: October 13, 2022Applicant: NexGen Power Systems, Inc.Inventors: Clifford Drowley, Andrew P. Edwards, Hao Cui, Subhash Srinivas Pidaparthi, Michael Craven, David DeMuynck
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Publication number: 20220328476Abstract: A vertical, fin-based field effect transistor (FinFET) device includes an array of individual FinFET cells. The array includes a plurality of rows and columns of separated fins. Each of the separated fins is in electrical communication with a source contact. The vertical FinFET device also includes one or more rows of first inactive fins disposed on a first set of sides of the array of individual FinFET cells, one or more columns of second inactive fins disposed on a second set of sides of the array of individual FinFET cells, and a gate region surrounding the individual FinFET cells of the array of individual FinFET cells, the first inactive fins, and the second inactive fins.Type: ApplicationFiled: March 29, 2022Publication date: October 13, 2022Applicant: NexGen Power Systems, Inc.Inventors: Clifford Drowley, Andrew P. Edwards, Hao Cui, Subhash Srinivas Pidaparthi
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Publication number: 20220293530Abstract: A method of forming alignment marks includes providing a III-V compound substrate having a device region and an alignment mark region, forming a hardmask layer having a first set of openings on the alignment mark region exposing a first surface portion of the III-V compound substrate and a second set of openings on the device region exposing a second surface portion of the III-V compound substrate, etching the exposed surface of the III-V compound substrate using the hardmask layer as a mask to form a plurality of trenches, and epitaxially regrowing a semiconductor layer in the trenches to form the alignment marks extending to a predetermined height over the processing surface of the III-V compound substrate.Type: ApplicationFiled: March 29, 2022Publication date: September 15, 2022Applicant: NexGen Power Systems, Inc.Inventors: Clifford Drowley, Ray Milano, Robert Routh, Subhash Srinivas Pidaparthi, Andrew P. Edwards