Abstract: A semiconductor device has an active area and a terminal area surrounding the active area and includes a base region, a plurality of annular subregions, an insulating layer provided with a plurality of insulating layer openings, and a first conductive layer. The plurality of annular subregions includes a first annular subregion in contact with the base region. The first annular subregion includes a plurality of annular structures in contact with each other. All the annular structures contact the first conductive layer through the corresponding insulating layer openings. The base region, the annular subregions, and the annular structures have a second conductivity type.

Abstract: A semiconductor device includes an insulated-gate bipolar transistor (IGBT) structure and a metal-oxide-semiconductor (MOS) transistor structure integrated in a wafer. The MOS transistor structure is connected in parallel with the IGBT structure. A thickness of a trench insulating layer in the MOS transistor structure is less than a thickness of a trench insulating layer in the IGBT structure.

Abstract: A semiconductor device includes a semiconductor layer with a first and second surface. The semiconductor layer includes: a source region and gate regions. The source region includes an N-type source region, a P-type body layer, and a carrier storage layer. Each gate region includes a gate oxide layer and polysilicon. The gate oxide layer surrounds a side wall and bottom of the polysilicon. The source region is arranged between adjacent gate regions and contacts the gate oxide layers. The gate oxide layer extends to a first depth. The bottom of the polysilicon is located at a second depth away from the first surface. A part of the gate oxide layer has a constant thickness in a transverse direction and another part gradually increases thickness in the transverse direction. The third depth is within a range of a depth where the first P-type body layer is located.

Abstract: A controller of a synchronous rectifier of a synchronous flyback converter is presented. The synchronous rectifier includes a switch that is switchable by the controller. The controller includes an adaptive slew rate detection circuit that is configured to add a current to a base slew rate current depending on an off-time of the switch to obtain a slew rate current. The slew rate current determines a slew rate setting voltage. The controller is configured to turn on the switch of the synchronous rectifier depending on the slew rate setting voltage.

Abstract: The present disclosure has a substrate for power semiconductor packaging and a package containing such a substrate. The substrate includes: a first metal layer for contacting with a semiconductor device, a second metal layer for contacting with a heat dissipation device, an electrical insulation layer disposed between the first metal layer and the second metal layer, and a first graphene bulk layer disposed between the electrical insulation layer and the first metal layer, a first surface of the first graphene bulk layer is in contact with a first surface of the first metal layer, and a second surface of the first graphene bulk layer opposite to the first surface is in contact with a first surface of the electrical insulation layer. Compared to the conventional substrate, the novel substrate of the present disclosure exhibits much lower thermal resistance, higher mechanical strength, and enhanced corrosion resistance.

Abstract: An electronic rectifier circuit for adaptive gate voltage regulation of a synchronous rectifier field-effect transistor is provided, the electronic rectifier circuit is configured to clamp a drain-source voltage of the SR FET to a first regulation voltage while the SR FET is switched on for less than a threshold time in a current switching cycle, and the electronic rectifier circuit is configured to clamp the Vds of the SR FET to a second regulation voltage while the SR FET is switched on for more than the threshold time in the current switching cycle, the threshold time is configured as a portion of time that the SR FET was switched on in one or more previous switching cycles, and Vreg2 is smaller than Vreg1.

Abstract: A parallel multiple-port system is provided, including a plurality of ports, a plurality of processors, and a memory storing software code which, when executed by the plurality of processors causes the processors to control the plurality of ports. A first processor is configured to control a first port. A second processor is configured to control a second port. The software code includes a common software code portion relevant to the plurality of ports and for execution by the plurality of processors. The software code further includes a port specific code portion including first configuration data for the first port and for execution by the first processor, and second configuration data for the second port and for execution by the second processor. The present application can advantageously be applied to parallel multi-port charging systems.

Abstract: A power module package and method of manufacture is provided, and includes: a substrate, a first and a second trace insulated from each other on the substrate, and at least one semiconductor die. Each die includes a first and a second electrode pad and a control electrode pad. The first pad and the control pad are on a first surface of the die facing the substrate, and the second pad is on a second surface of the die facing away from the substrate. The first pad is connected to the first trace, and the control pad is connected to the second trace. The package further includes a first electrode contact connected to the first trace, a second electrode contact connected to the second electrode pad of each die from a side of each die away from the substrate, and a control electrode contact connected to the second trace.

Abstract: A current limiter and a charge pump regulator including the current limiter are provided. The charge pump regulator converts an input voltage to an output voltage and includes a feedback loop including a first transistor for regulating a discharge current from the charge pump regulator. The current limiter limits the current provided by the charge pump regulator. The current limiter includes a sampling block configured to sample a first drain-source voltage of the first transistor and hold it as a reference drain-source voltage; an adaptive tracking block configured to receive the reference drain-source voltage, and to generate a maximum voltage based on the reference drain-source voltage, so that the maximum voltage tracks the reference drain-source voltage; and a voltage clamp block configured to clamp a feedback voltage to the maximum voltage, and to provide the clamped voltage as a first gate-source voltage of the first transistor.

Abstract: A reference voltage generating circuit is provided, including a first depletion type metal-oxide semiconductor field-effect transistor (MOSFET), a first enhancement type MOSFET, a reference voltage output connected between the first depletion type MOSFET and the first enhancement type MOSFET, and a second depletion type MOSFET.

Abstract: A reference voltage generating circuit is provided, including a first depletion type metal-oxide semiconductor field-effect transistor (MOSFET), a first enhancement type MOSFET, a reference voltage output connected between the first depletion type MOSFET and the first enhancement type MOSFET, and a second depletion type MOSFET.

Abstract: A semiconductor device having cells is provided, with each cell including a gate. The device includes a gate pad, a gate busbar and gate lines. The busbar connects the gate pad to the gate lines, the gate lines connect the gate busbar to the gates of the cells, and each of the gate lines is disposed along a first axis. The gate busbar includes first portions each disposed along a second axis, and the second axis intersects with the first axis. The first portions are spaced apart from each other to divide the semiconductor device into emitter segments. Lengths of the emitter segments along the first axis changes with distances of the segments from the gate pad, so that gate signals arriving at the gates of the cells from the gate pad via the gate busbar and the gate lines are substantially consistent.

Abstract: A semiconductor device having cells is provided, with each cell including a gate. The device includes a gate pad, a gate busbar and gate lines. The busbar connects the gate pad to the gate lines, the gate lines connect the gate busbar to the gates of the cells, and each of the gate lines is disposed along a first axis. The gate busbar includes first portions each disposed along a second axis, and the second axis intersects with the first axis. The first portions are spaced apart from each other to divide the semiconductor device into emitter segments. Lengths of the emitter segments along the first axis changes with distances of the segments from the gate pad, so that gate signals arriving at the gates of the cells from the gate pad via the gate busbar and the gate lines are substantially consistent.

Abstract: The present disclosure relates to a power converter and to a buck DC-to-DC power converter, such as a constant-on-time (COT) Buck DC-to-DC power converter. Additionally, a COT Buck DC-to-DC converter is provided which has a seamless transition between the normal operation mode and the 100% duty operation mode.

Abstract: According to an aspect of the present disclosure, a drive voltage generator for driving a GaN high electron mobility transistor is provided. According to another aspect there is provided a GaN high electron mobility transistor unit including a GaN high electron mobility transistor, and a drive voltage generator connected to the GaN high electron mobility transistor. A method for generating a drive voltage for a GaN high electron mobility transistor is also provided.

Abstract: A voltage gate driver for a semiconductor-based transistor is provided, including a voltage generator circuit arranged for receiving a drive voltage, the voltage generator circuit includes a capacitor connected in series with a Zener diode, a cathode of the Zener diode is arranged to be connected to a gate of the semiconductor-based transistor and a bias current circuit, connected in parallel over the capacitor, the bias current circuit includes a switch and is arranged to provide a bias current to the cathode of the Zener diode based on a state of the switch, and the bias current circuit is arranged to provide the bias current to the cathode of the Zener diode when the switch is in a closed state, and arranged to prevent provision of the bias current to the cathode of the Zener diode when the switch is in an open state.

Abstract: The disclosure provides power semiconductor modules and their assembling methods. The module includes a heat-dissipation contact area, a housing and a press-on element. One of the housing and the press-on element includes a rail portion, while the other includes a rail cooperating portion. The housing and the press-on element respectively includes a first limiting portion and a first limiting cooperating portion. The rail cooperating portion can be inserted into the rail portion and slides on the rail portion in the direction toward or away from the plane where the heat-dissipation contact area is located, so that the press-on element could move from the separation position to the mounted position connected with the housing. The rail portion can cooperate with the rail cooperating portion to prevent the press-on element from moving relative to the housing in the direction parallel to the plane where the heat-dissipation contact area is located.

Abstract: A cell structure of an insulated gate bipolar transistor (IGBT) with a control gate and a carrier storage layer, is provided including: an N-type drift layer with a first surface, an active region on a second surface opposing the first and an N-type storage layer, a P-type body layer and an N-type doped layer sequentially stacked in the active region from the first to the second surface, gate trench bodies, each of which extends from the second to the first surface in a first direction perpendicular to the first surface and contacts the N-type drift layer, and each of the at least three gate trench bodies is a gate trench or a control gate trench. A sidewall of the gate trench is in contact with the active region, and a sidewall of the control gate trench is in contact with the P-type layer but not with the N-type layer.

Abstract: A semiconductor device and a manufacturing method thereof is provided. The device includes a semiconductor layer having a first and second surface opposing each other; a trench gate in the semiconductor layer, extends in a first direction parallel to the first and second surface, and from the first surface to an interior of the layer, and has a gate open end distant from the second surface; a source region of a first conductivity type and a channel region of a second conductivity type, orthographic projections of the source region and the channel region on the second surface at least partially overlap with each other in a depth direction of the trench gate, the source region having a source open end distant from the second surface, and the farther the source open end is from the second surface, the smaller a width of the source open end in the second direction.

Abstract: A load switch and a power system are provided. The load switch includes a power input terminal, a power output terminal, a voltage-current conversion circuit, a capacitor and a comparator. The power input terminal is configured to receive an input voltage. The power output terminal is configured to provide an output voltage. The voltage-current conversion circuit includes a first input terminal, a second input terminal and a current difference output terminal. The first input terminal and the second input terminal are connected to the power output terminal and the power input terminal, respectively, and configured to receive the output voltage and the input voltage, respectively. A current difference characterizing a voltage difference between the output voltage and the input voltage is output at the current difference output terminal.