Abstract: A reference voltage generating circuit is provided, including a first depletion type metal-oxide semiconductor field-effect transistor (MOSFET), a first enhancement type MOSFET, a reference voltage output connected between the first depletion type MOSFET and the first enhancement type MOSFET, and a second depletion type MOSFET.

Abstract: A reference voltage generating circuit is provided, including a first depletion type metal-oxide semiconductor field-effect transistor (MOSFET), a first enhancement type MOSFET, a reference voltage output connected between the first depletion type MOSFET and the first enhancement type MOSFET, and a second depletion type MOSFET.

Abstract: A semiconductor device having cells is provided, with each cell including a gate. The device includes a gate pad, a gate busbar and gate lines. The busbar connects the gate pad to the gate lines, the gate lines connect the gate busbar to the gates of the cells, and each of the gate lines is disposed along a first axis. The gate busbar includes first portions each disposed along a second axis, and the second axis intersects with the first axis. The first portions are spaced apart from each other to divide the semiconductor device into emitter segments. Lengths of the emitter segments along the first axis changes with distances of the segments from the gate pad, so that gate signals arriving at the gates of the cells from the gate pad via the gate busbar and the gate lines are substantially consistent.

Abstract: A semiconductor device having cells is provided, with each cell including a gate. The device includes a gate pad, a gate busbar and gate lines. The busbar connects the gate pad to the gate lines, the gate lines connect the gate busbar to the gates of the cells, and each of the gate lines is disposed along a first axis. The gate busbar includes first portions each disposed along a second axis, and the second axis intersects with the first axis. The first portions are spaced apart from each other to divide the semiconductor device into emitter segments. Lengths of the emitter segments along the first axis changes with distances of the segments from the gate pad, so that gate signals arriving at the gates of the cells from the gate pad via the gate busbar and the gate lines are substantially consistent.

Abstract: The present disclosure relates to a power converter and to a buck DC-to-DC power converter, such as a constant-on-time (COT) Buck DC-to-DC power converter. Additionally, a COT Buck DC-to-DC converter is provided which has a seamless transition between the normal operation mode and the 100% duty operation mode.

Abstract: According to an aspect of the present disclosure, a drive voltage generator for driving a GaN high electron mobility transistor is provided. According to another aspect there is provided a GaN high electron mobility transistor unit including a GaN high electron mobility transistor, and a drive voltage generator connected to the GaN high electron mobility transistor. A method for generating a drive voltage for a GaN high electron mobility transistor is also provided.

Abstract: A voltage gate driver for a semiconductor-based transistor is provided, including a voltage generator circuit arranged for receiving a drive voltage, the voltage generator circuit includes a capacitor connected in series with a Zener diode, a cathode of the Zener diode is arranged to be connected to a gate of the semiconductor-based transistor and a bias current circuit, connected in parallel over the capacitor, the bias current circuit includes a switch and is arranged to provide a bias current to the cathode of the Zener diode based on a state of the switch, and the bias current circuit is arranged to provide the bias current to the cathode of the Zener diode when the switch is in a closed state, and arranged to prevent provision of the bias current to the cathode of the Zener diode when the switch is in an open state.

Abstract: A cell structure of an insulated gate bipolar transistor (IGBT) with a control gate and a carrier storage layer, is provided including: an N-type drift layer with a first surface, an active region on a second surface opposing the first and an N-type storage layer, a P-type body layer and an N-type doped layer sequentially stacked in the active region from the first to the second surface, gate trench bodies, each of which extends from the second to the first surface in a first direction perpendicular to the first surface and contacts the N-type drift layer, and each of the at least three gate trench bodies is a gate trench or a control gate trench. A sidewall of the gate trench is in contact with the active region, and a sidewall of the control gate trench is in contact with the P-type layer but not with the N-type layer.

Abstract: The disclosure provides power semiconductor modules and their assembling methods. The module includes a heat-dissipation contact area, a housing and a press-on element. One of the housing and the press-on element includes a rail portion, while the other includes a rail cooperating portion. The housing and the press-on element respectively includes a first limiting portion and a first limiting cooperating portion. The rail cooperating portion can be inserted into the rail portion and slides on the rail portion in the direction toward or away from the plane where the heat-dissipation contact area is located, so that the press-on element could move from the separation position to the mounted position connected with the housing. The rail portion can cooperate with the rail cooperating portion to prevent the press-on element from moving relative to the housing in the direction parallel to the plane where the heat-dissipation contact area is located.

Abstract: A semiconductor device and a manufacturing method thereof is provided. The device includes a semiconductor layer having a first and second surface opposing each other; a trench gate in the semiconductor layer, extends in a first direction parallel to the first and second surface, and from the first surface to an interior of the layer, and has a gate open end distant from the second surface; a source region of a first conductivity type and a channel region of a second conductivity type, orthographic projections of the source region and the channel region on the second surface at least partially overlap with each other in a depth direction of the trench gate, the source region having a source open end distant from the second surface, and the farther the source open end is from the second surface, the smaller a width of the source open end in the second direction.

Abstract: A load switch and a power system are provided. The load switch includes a power input terminal, a power output terminal, a voltage-current conversion circuit, a capacitor and a comparator. The power input terminal is configured to receive an input voltage. The power output terminal is configured to provide an output voltage. The voltage-current conversion circuit includes a first input terminal, a second input terminal and a current difference output terminal. The first input terminal and the second input terminal are connected to the power output terminal and the power input terminal, respectively, and configured to receive the output voltage and the input voltage, respectively. A current difference characterizing a voltage difference between the output voltage and the input voltage is output at the current difference output terminal.

Abstract: A semiconductor device and a method for manufacturing the same is provided. The semiconductor device includes: a semiconductor body having a first surface and a second surface, the semiconductor body includes: a depletion region, a drift region having a first conductivity type, an island region having the first conductivity type, a buffer region having the first conductivity type, the drift region is more proximal to the first surface of the semiconductor body than the buffer region, the depletion region is located within the drift region, and the island region is located within the drift region, an ion concentration of the first conductivity type of the island region is higher than an ion concentration of the first conductivity type of the drift region.

Abstract: A package structure for a power semiconductor device is provided, including: a substrate; two or more semiconductor dies on the substrate, each of the semiconductor dies includes a first power switching pad, a second power switching pad and a gate; a gate control conductive trace, a first power switching contact and a second power switching contact are further arranged on the substrate, the gate control conductive trace is connected to each of the semiconductor dies via a bonding component, and the bonding component connecting a first semiconductor die to the gate control conductive trace is sandwiched between circuit lines formed by connecting the second power switching pads of the first semiconductor die and the neighboring second semiconductor die, to second power switching contact of the substrate.

Abstract: This disclosure provides a design method for a radiator of a vehicle power module. The design method includes: selecting a plurality of specific values from the possible value ranges of the first distance D1, the second distance D2 and the radius R, respectively, to form different combinations of the plurality of specific values, performing simulation calculations on the different combinations, and obtaining a temperature rise ?Tj and a pressure drop ?Pf corresponding to each combination to form a plurality of samples; through a response surface method, fitting explicit functions of the temperature rise ?Tj and the pressure drop ?Pf with the first distance D1, the second distance D2 and the radius R as dependent variables; and through a multi-objective optimization, determining the first distance D1, the second distance D2 and the radius R with an optimization objective that the temperature rise ?Tj and the pressure drop ?Pf are simultaneously minimized.