Abstract: A computing grid including an interconnect network including input ports and output ports; a plurality of egress ports; a plurality of configurable data routing junctions; a plurality of logical elements interconnected using the plurality of configurable data routing junctions; a plurality of ingress ports. In an embodiment at least one compute graph is projected onto the computing grid as a configuration of various elements of the computing grid.

Abstract: A method for runtime optimization of a configurable processing architecture are disclosed. The method comprises receiving a plurality of calls for running at least one function; identifying at least one pattern among the plurality of received calls; and based on the at least one pattern, manipulating at least a portion of the configurable processing architecture, to compute the least one function.

Abstract: A method for cache coherency in a reconfigurable cache architecture is provided. The method includes receiving a memory access command, wherein the memory access command includes at least an address of a memory to access; determining at least one access parameter based on the memory access command; and determining a target cache bin for serving the memory access command based in part on the at least one access parameter and the address.

Abstract: A method for implementing locking primitive in a computing architecture is provided. In an embodiment, the method includes receiving a first request to lock operation from a special hardware cell of the computing architecture from a first thread at a first-time pointer; receiving a second request from a second thread at a second-time pointer to a lock operation from the special hardware cell, wherein the first-time pointer is earlier than the second-time pointer; enabling the first thread to read from the special hardware cell and continuing execution of the first thread; and upon identification of an unlock request by the first thread, enabling the second thread to lock from the special hardware cell and continuing execution of the second thread.