Abstract: A digital circuit simulator is provided that combines the speed of a single pass simulator with the probabalistic analysis previously available only through lengthy iteration, and that avoids the extensive reporting of false errors typical to single pass simulators. The simulator represents signal level transitions and component gate delays by probability histograms. Circuit operation is divided into events, each of which is the propagation through a single component of transitions in one or more input signals to the component. Signal propagation through a component is analyzed using component models, which are provided for a variety of basic components; more complex components are represented by decomposing them into a corresponding structure of basic components. Each event is analyzed using the histograms for the input signals and for the component gate delay.Signal conflicts due to timing problems between the various inputs to a component are identified and reported.