Abstract: A silicon wafer for an electronic component, having an epitaxially grown silicon layer on a carrier substrate and the silicon layer is removed as a silicon wafer from the carrier substrate, in which at least one p-dopant and at least one n-dopant are introduced into the silicon layer during the epitaxial growth. The dopants are introduced into the silicon layer such that the silicon layer is formed having an electrically active p-doping and an electrically active n-doping, each greater than 1×1014 cm?3.

Abstract: A method for the continuous vapour deposition of silicon on substrates, including the following steps: a) introducing at least one substrate into a reaction chamber; b) introducing a process gas and at least one gaseous silicon precursor compound into the reaction chamber; c) forming a gaseous mixture of at least one silicon-based intermediate product coexisting with the gaseous silicon precursor compound and the process gas; d) forming a silicon layer by vapour deposition of silicon from the gaseous silicon precursor compound and/or the silicon-based intermediate product on the substrate; e) discharging an excess of the gaseous mixture from the reaction chamber; f) returning at least one of the constituents of the excess of the gaseous mixture, selected from the silicon precursor compound, the silicon-based intermediate product and/or the process gas into the reaction chamber, wherein introducing the gaseous silicon precursor compound into the reaction chamber is regulated such that the molar ratio of the si

Abstract: A process for removal of impurities, in particular of dopants, from chlorosilanes which includes the following steps: (a) heating a deposition surface (3); (b) contacting the heated deposition surface (3) with at least one gaseous chlorosilane mixture, the gaseous chlorosilane mixture including at least one chlorosilane and at least one impurity, in particular at least one dopant; (c) at least partially removing the impurity, in particular the dopant, by forming polycrystalline silicon depositions on the deposition surface (3), the polycrystalline silicon depositions being enriched with the impurity, in particular with the dopant; (d) discharging the purified gaseous chlorosilane mixture; (e) contacting the heated deposition surface (3) with an etching gas to return the polycrystalline silicon depositions and the impurity, in particular the dopant, into the gas phase to form a gaseous etching gas mixture; and (f) discharging the gaseous etching gas mixture.

Abstract: A method for producing a wafer layer, including the method steps of: A) providing a carrier element; B) making the carrier element porous on at least one surface in order to produce a separating layer; C) applying a wafer layer to the separating layer of the carrier element by epitaxy; and D) detaching the wafer layer from the carrier element, with method steps B to D being repeated at least once, preferably multiple times, with the carrier element. The method step A includes the additional method steps of: A1) providing a carrier substrate; and A2) applying a seed layer to at least one surface and at least one lateral face of the carrier substrate by epitaxy in order to produce the carrier element. A carrier element for producing a wafer layer and an intermediate product are also provided.

Abstract: An apparatus for etching one side of a semiconductor layer of a workpiece, including at least one etching basin for receiving an electrolyte, a first electrode which is provided for electrically contacting the electrolyte located in the etching basin, a second electrode which is provided for electrically contacting the semiconductor layer, a electrical power source which is electrically conductively connected to the first and the second electrodes for generating an etching current, and a transport apparatus for transporting the workpiece relative to the etching basin such that a semiconductor layer etching face to be etched can be wetted by the electrolyte in the etching basin.

Abstract: A process chamber guide, designed for linearly guiding a substrate carrier that can be displaced in the process chamber guide in a direction of guidance such that by displacement of the substrate carrier in a process position, an at least regional demarcation of a process chamber guide can be formed by the process chamber guide and substrate carrier. The invention is characterized in that the process chamber guide has a roller bearing for the substrate support and at least one sealing surface, which extends parallel to the direction of guidance and is designed and arranged in such a way that, whenever the substrate carrier arranged in the process chamber guide is in a process position, the sealing surface is spaced apart less than 1 mm from the substrate carrier. The invention further relates to a process chamber and to a method for guiding a substrate carrier in a processing position.

Abstract: An apparatus for etching one side of a semiconductor layer of a workpiece, including at least one etching basin for receiving an electrolyte, a first electrode which is provided for electrically contacting the electrolyte located in the etching basin, a second electrode which is provided for electrically contacting the semiconductor layer, a electrical power source which is electrically conductively connected to the first and the second electrodes for generating an etching current, and a transport apparatus for transporting the workpiece relative to the etching basin such that a semiconductor layer etching face to be etched can be wetted by the electrolyte in the etching basin.

Abstract: A silicon wafer for an electronic component, having an epitaxially grown silicon layer on a carrier substrate and the silicon layer is removed as a silicon wafer from the carrier substrate, in which at least one p-dopant and at least one n-dopant are introduced into the silicon layer during the epitaxial growth. The dopants are introduced into the silicon layer such that the silicon layer is formed having an electrically active p-doping and an electrically active n-doping, each greater than 1×1014 cm?3.

Abstract: A method for producing a silicon wafer for an electronic component, having the method step of epitaxially growing of a silicon layer on a carrier substrate and removing the silicon layer as a silicon wafer from the carrier substrate, in which at least one p-dopant and at least one n-dopant are introduced into the silicon layer during the epitaxial growth. The dopants are introduced into the silicon layer such that the silicon layer is formed having an electrically active p-doping and an electrically active n-doping, each greater than 1×1014 cm?3.

Abstract: An apparatus for etching one side of a semiconductor layer, including at least one etching tank for receiving an electrolyte, a first electrode, which is arranged to make electrical contact with the electrolyte located in the etching tank during use, at least a second electrode, which is arranged to make indirect or direct electrical contact with the semiconductor layer, at least one electric current source, which is electrically conductively connected to the first and the second electrode to produce an etching current, and at least one transport apparatus for transporting the semiconductor layer relative to the etching tank in such a way that substantially only an etching side of the semiconductor layer that is to be etched can be wetted by the electrolyte located in the etching tank during use.

Abstract: A method for arranging a plurality of semiconductor seed substrates on a carrier element, in which for applying a semiconductor layer to the seed substrates, the seed substrates are arranged on the carrier element by integral bonding. A carrier element having integrally bonded seed substrates for coating with a semiconductor layer is also provided.

Abstract: A process for removal of impurities, in particular of dopants, from chlorosilanes which includes the following steps: (a) heating a deposition surface (3); (b) contacting the heated deposition surface (3) with at least one gaseous chlorosilane mixture, the gaseous chlorosilane mixture including at least one chlorosilane and at least one impurity, in particular at least one dopant; (c) at least partially removing the impurity, in particular the dopant, by forming polycrystalline silicon depositions on the deposition surface (3), the polycrystalline silicon depositions being enriched with the impurity, in particular with the dopant; (d) discharging the purified gaseous chlorosilane mixture; (e) contacting the heated deposition surface (3) with an etching gas to return the polycrystalline silicon depositions and the impurity, in particular the dopant, into the gas phase to form a gaseous etching gas mixture; and (f) discharging the gaseous etching gas mixture.

Abstract: A method for producing a semiconductor layer (3), including the following method steps: A creating a release layer (2) on a carrier substrate (1); B applying a semiconductor layer (3) to the release layer (2); C detaching the semiconductor layer (3) from the carrier substrate. The invention is characterized in that, in method step A, the release layer (2) is created so as to fully cover at least a processing side of the carrier substrate, in that, in method step B, the semiconductor layer (3) is applied so as to fully cover the release layer (2) at least on the processing side and partially overlap one or more peripheral sides (5a, 5b) of the carrier substrate and in that, between method steps B and C, in a method step C0, regions of the semiconductor layer (3) that overlap a peripheral side are removed. The invention also relates to a semiconductor wafer, to a device for edge correction, to a detaching unit and to a device for producing a semiconductor layer.

Abstract: A method for arranging a plurality of semiconductor seed substrates on a carrier element, in which for applying a semiconductor layer to the seed substrates, the seed substrates are arranged on the carrier element by integral bonding. A carrier element having integrally bonded seed substrates for coating with a semiconductor layer is also provided.

Abstract: A method for producing a silicon wafer for an electronic component, having the method step of epitaxially growing of a silicon layer on a carrier substrate and removing the silicon layer as a silicon wafer from the carrier substrate, in which at least one p-dopant and at least one n-dopant are introduced into the silicon layer during the epitaxial growth. The dopants are introduced into the silicon layer such that the silicon layer is formed having an electrically active p-doping and an electrically active n-doping, each greater than 1×1014 cm?3.

Abstract: An apparatus for etching one side of a semiconductor layer, including at least one etching tank for receiving an electrolyte, a first electrode, which is arranged to make electrical contact with the electrolyte located in the etching tank during use, at least a second electrode, which is arranged to make indirect or direct electrical contact with the semiconductor layer, at least one electric current source, which is electrically conductively connected to the first and the second electrode to produce an etching current, and at least one transport apparatus for transporting the semiconductor layer relative to the etching tank in such a way that substantially only an etching side of the semiconductor layer that is to be etched can be wetted by the electrolyte located in the etching tank during use.

Abstract: A method for producing a semiconductor layer (3), including the following method steps: A creating a release layer (2) on a carrier substrate (1); B applying a semiconductor layer (3) to the release layer (2); C detaching the semiconductor layer (3) from the carrier substrate. The invention is characterized in that, in method step A, the release layer (2) is created so as to fully cover at least a processing side of the carrier substrate, in that, in method step B, the semiconductor layer (3) is applied so as to fully cover the release layer (2) at least on the processing side and partially overlap one or more peripheral sides (5a, 5b) of the carrier substrate and in that, between method steps B and C, in a method step C0, regions of the semiconductor layer (3) that overlap a peripheral side are removed. The invention also relates to a semiconductor wafer, to a device for edge correction, to a detaching unit and to a device for producing a semiconductor layer.