Abstract: The present invention aims to provide an etching solution composition which enables to etch a metal film in a controllable manner, form a desired definite tapered shape, and obtain a smooth surface without causing etching solution exudation trace. Said problems have been solved by the present invention, which is an etching solution composition for etching metal films containing one or more surfactants selected from the group consisting of alkyl sulfate or perfluoroalkenyl phenyl ether sulfonic acid and the salts thereof.
Abstract: A manufacturing method of this invention has an ion-implantation process for threshold voltage adjustment of an MOS transistor, including a process to form a first well of an opposite conductivity type in a substrate of one conductivity type, to form a second well of the opposite conductivity type having higher impurity concentration than that in the first well, under a region where a thin gate insulation film is formed, to form gate insulation films on the first well and the second well, each having a different thickness, to ion-implant first impurities of the one conductivity type into the wells of the opposite conductivity type under the condition that the impurities penetrate the gate insulation films of different thicknesses and to ion-implant second impurities of the one conductivity type into the second well of the opposite conductivity type under the condition that the second impurities penetrate the thin gate insulation film but do not penetrate the thick gate insulation film.
Type:
Grant
Filed:
November 27, 2002
Date of Patent:
November 9, 2004
Assignees:
Sanyo Electric Co., Ltd., Niigata Sanyo Electronics Co., Ltd.