Abstract: A linear voltage regulator includes a first driver stage coupled between the error amplifier and the pass transistor of the regulator. A first transistor of the first driver stage has a gate terminal connected to receive the error signal from the error amplifier. A gate terminal of the pass transistor is coupled to receive an output of the first driver stage. The linear voltage regulator includes a compensation circuit for frequency compensation, and a compensation adjustment circuit. The compensation adjustment circuit in the regulator senses a magnitude of the current through the first transistor of the first driver stage, and adjusts a parameter of the compensation circuit based on the magnitude of the sensed current. Sensing the current at the first driver stage provides an indication of the load current drawn from the regulator, and is used for controlling the location of a compensating zero introduced by the compensation circuit.

Abstract: A voltage regulator includes a slew-up circuit, a slew-down circuit and a transient response control circuit, and provides a regulated output voltage. The slew-up circuit is designed to couple a first node of the voltage regulator to a first constant reference potential upon occurrence of a first condition of the regulated output voltage. The slew-down circuit is designed to couple the first node to a second constant reference potential upon occurrence of a second condition of the regulated output voltage. The transient response control circuit is designed to disable the slew-up circuit and the slew-down circuit upon the rate of change of the regulated output voltage exceeding a predetermined rate. The first node is one of an output node and an output steering node of the voltage regulator. Transient response of the voltage regulator is accordingly improved.

Abstract: A device includes a first oscillator, a second oscillator and a frequency comparison block. The first oscillator includes a first LC tank circuit and is designed to generate first sustained oscillations at a first resonant frequency. The second oscillator includes a second LC tank circuit and is designed to generate second sustained oscillations at a second resonant frequency. The frequency comparison block is designed to perform a comparison of the frequencies of the second sustained oscillations and the first sustained oscillations to determine a change in inductance in one of a first inductor of the first LC tank circuit and a second inductor of the second LC tank circuit. One of the oscillators serves as a reference oscillator, and enables determination of the change in inductance to be immune to changes in environmental conditions.

Abstract: A fractional sampling-rate converter includes a first-in first-out (FIFO) buffer, a write logic, a read logic and a fractional interpolator. The write logic is designed to write input data samples into the FIFO at a first rate. The fractional interpolator is coupled to receive the input data samples from the FIFO and is designed to generate corresponding interpolated data samples as an output of the fractional sampling-rate converter at a second rate. The read logic is designed to cause input data samples in the FIFO buffer to be transferred to the fractional interpolator. A ratio of the second rate and the first rate is a fractional number greater than one.

Abstract: A power supply includes a first DC-DC converter coupled to receive power from a first power source, a second DC-DC converter coupled to receive power from a second power source, and a control block. The first DC-DC converter is operable to generate a regulated power supply voltage on an output node of the power supply. The first power source has a maximum output current limit. The second DC-DC converter is also operable to generate a regulated power supply voltage on the output node. The control block is designed to generate the regulated power supply voltage based on both of the first DC-DC converter and the second DC-DC converter.