Patents Assigned to Nippon Board Computer Co., Ltd.
  • Patent number: 4922340
    Abstract: A method and an apparatus of compressing information content of multilevel digital image data having multilevel gradation value P (i, j) of each picture cell comprising means to determine an occurence frequency of individual gradation value from each gradation value P (i, j) in a predetermined image unit or to determine a difference value f(i, j) between gradation values of adjacent picture cells from multilevel image data of a predetermined image component as well as determining an occurrence frequency of individual difference values from the determined difference values f(i, j) in the image and means to code each multilevel gradation value P (i, j) or difference value f(i, j) by assigning a code having a lower bit number as the gradation or difference value has a higher occurrence frequency.
    Type: Grant
    Filed: January 3, 1989
    Date of Patent: May 1, 1990
    Assignee: Nippon Board Computer Co., Ltd.
    Inventor: Kiyoshi Iwai
  • Patent number: 4792753
    Abstract: A local area network protocol analyzer for analyzing packets or signal series running in a coaxial cable of a local area network and comprising a code/decoder to separate a packet received from the coaxial cable into a clock signal and a serial data signal, a receive signal processing section to convert the serial data signal into parallel data, a receive memory section to store the parallel data from the receive signal processing section in a receiving data memory section thereof and an output/input section to analyze and indicate the parallel data in the receiving data memory section and to input instruction signal to instruct the sections therefrom, the receive signal processing section including a control counter for controlling an address where the parallel data is stored in the receiving data memory and being counted up for every storing of the parallel data and the receive memory section including a managing data memory section under control of which a memory address pointer indicating where the packet
    Type: Grant
    Filed: February 19, 1987
    Date of Patent: December 20, 1988
    Assignee: Nippon Board Computer Co., Ltd.
    Inventor: Kiyoshi Iwai