Abstract: An image detection processing device which executes the processing at a high speed using a circuit constitution of a small scale best suited for calculating the centroid of an object, the circuit being arranged on the same chip as the image detection processing device. The image detection processing device or a so-called vision chip includes a plurality of image detection processing elements, and comprises a shift register for converting serial data representing the total sum or a portion of the pixel data into a first parallel data, an adder which receives the converted parallel data and outputs a second parallel data representing a first-order moment, and a serial divider which receives the first and second parallel data and divides them to produce serial data representing the centroid coordinates, featuring a circuit constitution of a small scale and realizing a high-speed processing.

Abstract: A frequency synthesizer comprises a digital/analog converter which sequentially converts difference data of phase data indicating the phase of a reference signal to an analog value, a voltage signal generator which integrates the analog value converted by the digital/analog converter, thereby generating a voltage signal interpolating between signal levels corresponding to two time-sequential pieces of the phase data, a reference-timing-signal output section which outputs a reference timing signal indicating the specific phase of the reference signal at a timing when the signal level of the voltage signal generated by the voltage signal generator crosses a preset setting voltage, and a reset section which resets the voltage signal generated by the voltage signal generator to the setting voltage. Accordingly, the noise performance of an output signal from the frequency synthesizer is improved.

Abstract: A detection circuit 30 has a unit 30a for inputting a signal to be detected by synchronized wave detection, a unit 30b for inputting a standard signal for the signal to be detected and a unit 30c for inputting an offset signal applied on the signal to be detected. The offset signal is superimposed on the signal to be detected, which is then subjected to synchronized wave detection based on the standard signal.

Abstract: To provide a semiconductor nonvolatile storage device capable of applying distributed voltage efficiently to a ferroelectric capacitor in a semiconductor nonvolatile storage device having an MFMIS structure without enlarging a memory cell area and a method of fabricating the same, a ferroelectric nonvolatile storage element is constructed by a structure successively laminated with a first insulator layer (3), a first conductor layer (4), a ferroelectric layer (5) and a second conductor layer (6) on a channel region and is constructed by a structure having a third conductor (9) and a fourth conductor (10) respectively laminated on a source region and a drain region, in which the third conductor (9) and the fourth conductor (10) are opposed to each other via the first conductor layer (4) and a second insulator thin film (11).

Abstract: The present invention is to provide a power down circuit, which can configure a wide range of the voltage of the control signal regardless of the fluctuation of the power supply voltage. In the power down circuit 1, the drain of the first N channel MOS transistor M1, into which the control signal PD is input, is connected to the power supply VDD via the resistor R, and at the same time, connected to the gate of the second N channel MOS transistor M2, the source of the second N channel MOS transistor M2 being connected to the gate of the N channel MOS transistor M4, to which the bias voltage VB is supplied, the drain of the N channel MOS transistor M4 being connected to the power supply VDD via the drain of the P channel MOS transistor M3, when the first N channel MOS transistor M1 is turned on/off by the control signal PD, the second N channel MOS transistor M2 is turned off/on, and the bias circuit 2 is operated under a normal condition when it is off, and comes into a power down state when it is on.

Abstract: A class D amplifier capable of compressing a dynamic range and reproduction by changing on a real time basis a modulation ratio to a non-linear ratio in accordance with amplitude of an input signal.

Abstract: Folding noises into signal bands are reduced and steeper cutoff characteristics are achieved without any increase in the scale of the circuit of a decimation filter attributable to the order of the filter coefficients and the bit precision of the same. Smaller attenuations are achieved in regions that do not contribute to folding noises, and filter coefficients are used to primarily attenuate signal components in regions contributing to folding noises and having a certain band width located about frequencies that are integral multiples of a decimated sampling frequency of 8 fs, thereby reducing folding noises compared to the prior art. Attenuations smaller than those in the prior art are achieved in other regions that do not contribute to folding noises to allow the filter coefficients to be used to make cutoff characteristics steeper accordingly, thereby achieving steeper cutoff characteristics while keeping folding noises at the level of the prior art.

Abstract: An image detection processor of the present invention enhances the processing speed of the calculation of the center of gravity or the like of a target with a simple constitution. The image detection processor arranges a plurality of image detection processing elements 1-1 to 1-64 on a plane. Each image detection processing element includes an adder circuit 15 which converts an output of a photoelectric conversion part 5 into digital signals and can receive the digital signals as an input in a matrix form. Cumulative adders are constituted by connecting the adder circuits 15 for respective rows. Series adders 2-1 to 2-8 which are connected in series respectively receive outputs of final stages of cumulative adders of respective rows as inputs and can cumulatively add these outputs.

Abstract: A detection circuit 30 has a unit 30a for inputting a signal to be detected by synchronized wave detection, a unit 30b for inputting a standard signal for the signal to be detected and a unit 30c for inputting an offset signal applied on the signal to be detected. The offset signal is superimposed on the signal to be detected, which is then subjected to synchronized wave detection based on the standard signal.

Abstract: It is provided a system for measuring a physical quantity based on a detection signal using a vibrator 1, a self-oscillating circuit 12A oscillating a driving vibration in the vibrator 1 and a detection circuit for outputting a detection signal from the vibrator 1. The self-oscillating circuit 12A comprises a current-voltage converter 3 and a low pass filter 25. The detection circuit comprises a charge amplifier circuit amplifying an output signal from the vibrator, and the current-voltage converter and the charge amplifier circuit are formed in a monolithic IC.

Abstract: Electric power consumed by a laser diode when an optical disk or magneto-optical disk is played back is reduced. A laser diode control circuit (6) causes the laser diode to emit continuously rather than intermittently, even if a PCK signal is supplied to the laser diode control circuit (6), when an optical display player or magneto-optical disk drive does not yet stabilize and is being pulled into a phase-locked state. When the focus is locked, the player is in a phase-locked state, and the operation is stable, a mode-switching circuit (9) included in the laser diode control circuit (6) switches the mode of operation from continuous operation to intermittent operation according to an FLOCK signal. The frequency of the PCK is multiplied by a frequency multiplier circuit (7), and the pulse width is adjusted by a pulse width-adjusting circuit (8). A laser diode driver circuit (10) produces intermittent current of this adjusted pulse width. The laser diode is started to emit intermittently.

Abstract: Provided is a circuit that has a simple circuit configuration and can detect zero values in a 1-bit digital signal irrespective of a recording medium such as SACD. DSD data forming the 1-bit digital signal are successively sent to a shift register (1) whose number of stages corresponds to the number of bits of an idle pattern such as “101010101” which appears when assuming a zero value. For example, the shift register (1) is an 8-bit shift register. An adder (2) sums up the values at each stages of the shift register (1). A zero decision circuit (4) produces an output indicating decision of zero if the sum value is half of the number of bits. A counter (5) keeps counting while the output indicating zero decision is being delivered. If the count value of the counter exceeds a given value, the counter produces an output indicating detection of a zero value.

Abstract: A ferroelectric non-volatile memory device that allows the coupling ratio to be increased and the effect of voltage distribution to the ferroelectric capacitor to be improved without increasing the area of the gate electrode of a detection MIS field effect transistor is provided. In a memory cell structure, a semiconductor including regions for a source, a channel, and a drain, a gate insulator on the channel region, a floating gate conductor, a ferroelectrics, and an upper electrode conductor are layered in this order. The structure includes a paraelectric capacitor having one end connected to the floating gate conductor and the other end connected to the source region.

Abstract: A transistor-type ferroelectric nonvolatile memory element having an MFMIS (metal-ferroelectric-metal-insulator-semiconductor) structure that can be highly densely integrated. The MFMIS transistor has a constitution in which the MFM (metal-ferroelectric-metal) structure and the MIS (metal-insulator-semiconductor) structure are stacked up and down on nearly the same area, and the lower MIS structure has means for increasing the effective area of the MIS capacitance. Means for increasing the effective area of the capacitor is a trench in the semiconductor substrate, ruggedness in the MIS structure or a MIN (metal-insulator-metal) structure.

Abstract: To provide a semiconductor nonvolatile storage device capable of applying distributed voltage efficiently to a ferroelectric capacitor in a semiconductor nonvolatile storage device having an MFMIS structure without enlarging a memory cell area and a method of fabricating the same, a ferroelectric nonvolatile storage element is constructed by a structure successively laminated with a first insulator layer (3), a first conductor layer (4), a ferroelectric layer (5) and a second conductor layer (6) on a channel region and is constructed by a structure having a third conductor (9) and a fourth conductor (10) respectively laminated on a source region and a drain region, in which the third conductor (9) and the fourth conductor (10) are opposed to each other via the first conductor layer (4) and a second insulator thin film (11).

Abstract: A CMOS inverter capable of operating at low voltages is provided. The gate of a p-channel MOS transistor and the gate of an n-channel MOS transistor are AC coupled to an input terminal via first and second capacitors, respectively. Signals whose amplitude centers are optimized according to the threshold voltages of the p- and n-channel MOS transistors by bias voltages from first and second variable voltage sources, respectively, are supplied to the gates of these MOS transistors. In consequence, the CMOS inverter can operate at high speeds at low power supply voltages without being affected by the threshold voltages.

Abstract: A temperature compensated oscillator keeping the area of a capacitor array and the bit number of a memory from increasing and allowing for high precision is provided. A adjusting method of such a resonator and an integrated circuit for temperature compensated oscillation are also provided. A capacitor array and a variable capacitance diode are connected and used as a load capacitance in an oscillation circuit, and the capacitance value of the former is digital-controlled and that of the latter is analog-controlled, so that the amount of compensation data necessary for the digital control is reduced and highly precise temperature compensation is permitted.

Abstract: To provide a semiconductor nonvolatile storage device capable of applying distributed voltage efficiently to a ferroelectric capacitor in a semiconductor nonvolatile storage device having an MFMIS structure without enlarging a memory cell area and a method of fabricating the same, a ferroelectric nonvolatile storage element is constructed by a structure successively laminated with a first insulator layer (3), a first conductor layer (4), a ferroelectric layer (5) and a second conductor layer (6) on a channel region and is constructed by a structure having a third conductor (9) and a fourth conductor (10) respectively laminated on a source region and a drain region, in which the third conductor (9) and the fourth conductor (10) are opposed to each other via the first conductor layer (4) and a second insulator thin film (11).

Abstract: A ferroelectric body transistor having a structure of MFMIS (conductor film) -ferroelectric film-conductor film-insulating film-semiconductor) including a gate insulator capacitor having an MIS structure, a low dielectric constant layer restraining layer interposed between an insulating film made of a material having a high inductive capacity of CeO2 and a semiconductor substrate to thereby restrain a low dielectric constant layer of SiO2 or the like from being produced at an interface between the insulating film and the semiconductor substrate and restrain a capacitance from being reduced. An area of the gate insulator capacitor can be reduced and highly integrated formation is provided.

Abstract: A semiconductor temperature detecting circuit use semiconductor temperature sensors each comprising bipolar transistors connected in a Darlington connection to provide a semiconductor temperature detecting circuit capable of automatically compensating for variations in fabrication of a reference voltage for comparing outputs of temperature sensors. The semiconductor temperature detecting circuit includes a first and a second semiconductor temperature sensor each having bipolar transistors connected in Darlington connection and respectively receiving different constant currents (I and nxI). Temperature detected is based on a corresponding relationship between a ratio of output voltages of the first and the second semiconductor temperature sensors and the temperature.