Abstract: It is an object to integrate storing functions at a high density and make it possible to perform a stable operation even at a low power supply voltage. A MOS transistor including a gate electrode and an n-type impurity region serving as a source-drain has a memory capacitor comprised by a dielectric film, a conductor, and an n-type impurity region opposing to the conductor through the dielectric film in a first trench formed in a p-type epitaxial layer beneath the gate electrode. With this structure, an area occupied by the MOS transistor and the memory capacitor can be minimized. Each unit memory cell is a two-transistor memory cell in which the drain and source of a MOS transistor supply a pair of complementary signals to a detection circuit. For this reason, a storing operation can be made reliable, and a stable operation can be realized, especially, at a low voltage.

Abstract: A burn-in board Vcc circuit changeover socket 204A and a GND circuit changeover socket 205A wich are arranged in a wiring area between terminals 1 to 7 of an IC socket 202 and resistors 203 corresponding to these terminals. A Vcc circuit changeover socket 204B and a GND circuit changeover socket 205B are arranged in a wiring area between terminals 8 to 14 of the IC socket 202 and resistors 203 corresponding to these terminals. A Vcc circuit changeover unit 206 is fitted, for example, in the Vcc circuit changeover socket 204A and a GND circuit changeover unit 207 is fitted, for example, in the GND circuit changeover socket 205B. A first electric potential (Vcc) is supplied to the terminals 5 and 7 of the IC socket 202, and a second electric potential (GND) is supplied to the terminals 12 and 14 of the IC socket 202. The Vcc circuit changeover unit 206 and the GND circuit changeover unit 207 may have different plug-in terminals according to kinds of ICs which may be made.

Abstract: A p-type high concentration doped region is formed in a p-type semiconductor substrate between a n-type doped region as part of an input protection circuit and another n-type doped region as part of internal circuitry. A plate is divided into two over the high concentration doped region. The high concentration doped region suppresses generation of a parasitic MOS transistor with the plate for a gate, one of the n-type doped regions for a source, and the other for a drain.

Abstract: A current sensing differential amplifier with high rejection of power supply variations and method for an integrated circuit memory device which allows the amplifier's differential voltage level and speed to track that of the sense amplifier supplying the information, thereby achieving the needed margin for critical synchronous timing. The reliability of the differential amplifier is also increased due to the provision of a larger differential signal and higher supply voltage levels. In a preferred embodiment, an n-channel transistor serves as a regulator with its drain terminal coupled to an unregulated supply voltage source ("V.sub.cc "). The gate of the transistor is then coupled to a regulated supply voltage ("V.sub.ccp ") which is a function of the voltage supply for the sense amplifier. The source of the transistor is connected to the sources of the p-channel transistors in the main amplifier which provide feedback to the main amplifier.

Abstract: Dielectric isolation in the bit-line direction is performed by a first trench filled with an insulator, dielectric isolation in the word-line direction is performed by a second trench filled with a conductive film serving as a field-shield electrode interposing an insulating film, and capacitors are formed on side walls of the second trench by the conductive film and a semiconductor substrate with the insulating film interposed therebetween. A high-density, large-scale DRAM is realized by combining the technologies of field-shield element isolation, trench element isolation, and side-wall capacitors in a trench. In this DRAM, the conductive film in a trench-capacitor structure serves as a field-shield electrode in a field-shield structure for dielectric isolation between memory cells. Since the capacitor forms a capacitance inside the semiconductor substrate on one side wall of the trench, high-density integration is possible.

Abstract: A lead frame includes a base, a substantially rectangular device hole formed in the base, an island formed in the device hole and offset a predetermined distance from the base, a plurality of inner leads arranged at predetermined intervals to extend toward a pair of opposing edges of the island, and suspension pins formed to extend toward a pair of edges of the island not opposing the end portions of the inner leads. The island is used to mount a semiconductor chip, and the suspension pins connect the island and the base. A pair of dummy leads extended from the base toward the island is formed on the both sides of at least one suspension pin. The distance from the side edge of the suspension pin to the side edge of the dummy lead is equal to or smaller than the distance from the end portions of the inner leads to the side edge of the island.

Abstract: An integrated circuit having a first and second bond pads, a latch circuit, and a voltage lead. Different configurations of the internal circuitry of the integrated circuit are selected by applying the voltage lead either to the first or second bond pads. This result is achieved because the latch circuit, coupled between the first and second bond pads, is capable of inverting the voltage response seen at the first bond pad.

Abstract: A wide range power supply for integrated circuits includes a voltage-down converter to receive the input supply voltage and generate a controlled low voltage signal. The circuit also includes a voltage-up converter which receives the controlled low voltage signal to generate a high voltage signal for high power circuits. Finally, a substrate bias generator is employed in the circuit to generate a substrate bias signal. Because the low power voltage is controlled, the high power voltage and the substrate bias signal are independent of any variations in input supply voltage. In alternate embodiments, the voltage-up converter or voltage-down converter can be disabled if the external supply voltage is controlled and maintained in at high or low voltage respectfully.

Abstract: A wide range power supply for integrated circuits includes a voltage-down converter to receive the input supply voltage and generate a controlled low voltage signal. The circuit also includes a voltage-up converter which receives the controlled low voltage signal to generate a high voltage signal for high power circuits. Finally, a substrate bias generator is employed in the circuit to generate a substrate bias signal. Because the low power voltage is controlled, the high power voltage and the substrate bias signal are independent of any variations in input supply voltage. In alternate embodiments, the voltage-up converter or voltage-down converter can be disabled if the external supply voltage is controlled and maintained in at high or low voltage respectfully.

Abstract: A counter circuit selectively generates counting sequences in binary and interleave counting modes. A counter is formed by 3 toggle flip-flops. The toggle signals are provided by a toggle control circuit which contains logic gates that are enabled or disabled based on the state of a mode select signal. In binary mode, output bits are permitted to be used to toggle higher order count stages. In interleave mode, the binary toggle signals are blocked, and another counter circuit counts toggle signals in the interleave sequence, which signals are passed by the toggle control circuit to toggle inputs of the main counter. The other counter circuit can be reset in response to a reset signal applied to a load enable input.

Abstract: A constant current source is used to provide a constant current to set a delay which defines the period of the output of the oscillator. The delay is preferably set by charging a capacitor with the constant current. Because the current is independent of variations in V.sub.CC and temperature, the capacitor will charge for a given period. Therefore, the frequency or period of oscillation will also be fixed and independent of variation in V.sub.CC or temperature. A current limiting circuit and latch are provided to generate an output which will be transmitted through one or a series of inverters. In an alternate embodiment, a differential amplifier is provided between the delay circuit and the current limiting circuit. This differential amplifier is typically needed in a case where VCC is not well-controlled to provide an output signal which has an appropriate voltage. A method of generating an oscillating output for refreshing a DRAM and a method for refreshing a DRAM are also disclosed.

Abstract: Positive feedback increases switching speeds and negative feedback prevents the voltage at the inputs from varying too far in a sense amplifier used to sense voltage differentials on bit lines or data lines of semiconductor memories, or elsewhere. Switching speeds improve without increased current consumption.

Abstract: Burst refresh mode circuitry is provided for a memory having cells in rows and columns, sense amplifiers and Latch N/Latch P driver circuitry, a RAS buffer, refresh counters, address buffers, row decoders, precharge circuitry producing shorting clocks, and a refresh detector circuit coupled to the Latch P circuitry to provide a restore finished (RF) signal indicative that a refresh cycle is substantially completed. Burst refresh mode entry circuitry detects proper conditions for entering burst refresh mode. An auto-refresh burst refresh mode circuit causes the RAS buffer to generate a new internal RAS signal. Burst refresh mode logic has counters to count the number of rows that have been refreshed. The system self-times the refreshing by responding to the restore finished signal. A delay circuit interposes a short delay for the precharge before another row is automatically refreshed in the burst refresh mode. Battery back-up mode circuitry is partially disabled.

Abstract: A high efficiency charge pump for low and wide voltage ranges. The charge pump includes main and secondary charge pumps, the secondary charge pump is employed to avoid the Vt.sub.N drop that the main charge pump exhibits. The secondary charge pump allows the main charge pump to pump to a theoretical maximum of 2 VCC, while maintaining an efficiency close to 40%.

Abstract: A constant current source is used to provide a constant current to set a delay which defines the period of the output of the oscillator. The delay is preferably set by charging a capacitor with the constant current. Because the current is independent of variations in V.sub.CC and temperature, the capacitor will charge for a given period. Therefore, the frequency or period of oscillation will also be fixed and independent of variation in V.sub.CC or temperature. A current limiting circuit and latch are provided to generate an output which will be transmitted through one or a series of inverters. In an alternate embodiment, a differential amplifier is provided between the delay circuit and the current limiting circuit. This differential amplifier is typically needed in a case where VCC is not well-controlled to provide an output signal which has an appropriate voltage. A method of generating an oscillating output for refreshing a DRAM and a method :for refreshing a DRAM are also disclosed.

Abstract: A voltage generator for low power applications includes a circuit for generating, controlling and maintaining a high voltage for low power applications in an integrated circuit. The circuit includes separate standby and active circuits for pumping V.sub.CCP of a DRAM under different circumstances. The standby and active circuits operate independently of one another, but may operate simultaneously, to pump charge to V.sub.CCP. The standby circuit is generally a low power circuit activated in response to power up and leakage current conditions to maintain V.sub.CCP. The active circuit is generally a larger circuit and can pump more current. The active circuit is generally responsive to the word lines being driven. Accordingly, the voltage generator can maintain V.sub.CCP while minimizing power consumption in DRAM.

Abstract: A method and apparatus for generating two control signals (LPB and LNB) to activate local sense amplifier driver transistors is described. The rise and fall times of these signals as well as their levels keep the sense speed and peak currents as constant as possible over the specified voltage and temperature ranges. This is achieved preferably by using current sources based on resistors to control the rise/fall times and current mirrors or modeling circuits to set the voltage levels. Preferably circuitry is provided to determine when LNB and LPB reach intermediate and full voltage levels. The timing is set to spread out the current peak into three separate smaller peaks.

Abstract: A memory device circuit that alters the input refresh addresses to access fewer memory cells to save power, or to address more memory cells to decrease the refresh time. The circuit contains a simple transistor configuration that blocks certain address bits, then substitutes active bits in their place to the address decoder. The circuit also includes a controller that is responsive to the memory device entering the refresh mode. When the device is used in refresh mode, the address bits may be passed unblocked to the address decoder for full user control.

Abstract: A reference voltage generator which compensates for temperature and V.sub.CC variations includes a constant current source and a MOS P-channel transistor. The constant current source provides a constant current over a wide range of V.sub.CC that corresponds to biasing a p-channel transistor in a region where its resistance is constant. The output of the current source is supplied to the P-channel transistor, which is in saturation. The constant current provides a constant voltage drop across the P-channel transistor. Hence, a stable reference voltage is generated. Temperature compensation is provided by biasing the P-channel transistor to saturation and supplying a constant current that the corresponds to biasing a p-channel transistor where the resistance is substantially constant over a temperature range. The current causes a voltage drop across the P-channel transistor to maintain a stable reference voltage.