Patents Assigned to NITERO PTY LTD.
  • Patent number: 9450620
    Abstract: A digital interface and control module and a multi-function digital bus for use in a wireless radio frequency receiver, transmitter, or transceiver that communicates over a millimeter-wave band at multi-gigabit speeds. The control module provides a low power, low cost, small form factor, and low pin-count solution for high-speed control of a multi-gigabit radio frequency circuitry. The control module may be used to steer an antenna array for beamforming including selecting different antennas and different phases in compliance with IEEE 802.11ad/WiGig specifications. The control module may also be used for individually controlling variable gain amplifiers and low noise amplifiers and for phase shift controls, gain settings, and other controls.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: September 20, 2016
    Assignee: Nitero Pty Ltd.
    Inventors: Sebastian Ahmed, Richard Steven Richmond, II
  • Patent number: 9264216
    Abstract: A method and apparatus for low power timing recovery is provided. In an embodiment, different gains are used to estimate timing errors during different portions of the data packet. In an embodiment, timing errors are only estimated during known sequences of a data packet. In further embodiments, errors are initially estimated independently in a first portion of the data packet in order to determine a phase shift between the errors. In the second portion of the data packet, the total error is derived from one estimated error and the phase shift between the errors.
    Type: Grant
    Filed: March 23, 2015
    Date of Patent: February 16, 2016
    Assignee: NITERO PTY LTD.
    Inventors: Ngoc Vinh Vu, Antonio Torrini
  • Patent number: 9231792
    Abstract: An adaptive equalization system and operating method thereof are disclosed herein. According to an embodiment, an apparatus comprises a plurality of equalizers and control logic to selectively enable one or more equalizers of the plurality of equalizers and disable one or more other equalizers of the plurality of equalizers based, at least in part, on a quality of the channel over which the signal is received. In another embodiment, the apparatus includes first control logic to select an equalizer for a header of a packet and second control logic to select an equalizer for a data payload of the packet.
    Type: Grant
    Filed: January 21, 2015
    Date of Patent: January 5, 2016
    Assignee: NITERO PTY LTD.
    Inventors: Antonio Torrini, Darren Rae Di Cera, Ngoc Vinh Vu