Abstract: A digital processor including both macro and micro instruction generators. The micro-instruction generator comprises a sequencer for generating instruction addresses, a memory for generating instructions in response to the addresses and a pipeline register adapted to receive the instructions for execution. The sequencer operates at a constant CLK 1 rate while the pipeline register operates at a variable CLK 2 rate; i.e., the occurrence of a branch instruction in the pipeline register operates to inhibit CLK 2 for one CLK 1 time so as to prevent loading for execution of the aborted sequential instruction during the loading of a new non-sequential instruction address. CLK 2 resumes upon the next CLK 1 signal to resume sequential operation. Special branch instructions are utilized to fetch macro-instructions from a pipelined system of macro-instruction registers. A two-tier synchronous arbitration system for memory requests is also disclosed.

Abstract: A multilevel video display control circuit. A plurality of current levels are developed in response to coded command signals (P1, P2, P3). The generated currents are summed together and converted to analog voltage signals (V25) to control the brightness of the pixels on the display. A contrast adjustment network (26) includes a first potentiometer (K1) for setting the magnitude of one of the currents at a desired level. A second potentiometer (K2) is provided for varying the magnitudes of the other current levels while maintaining the first current at the preset magnitude. Preferably, the magnitude of the first current is inversely varied with respect to other current levels.

Abstract: A method and apparatus for formatting a memory disk (10). Information is stored in compressed form in memory (32). Each sequentially different byte of information is accompanied by a numerical variable defining the number of times the byte is to be written on the disk (10). The numerical variable is loaded into a control counter (40) which is decremented every time the byte is written. The same byte is fetched from the memory (32) until the control counter (40) reaches zero.

Abstract: A voltage regulator network (10) for use in cooperation with a linear regulator device (18) to supply at least one regulated output voltage (20). A transformer (T1) includes first (N1) and second (N2) windings. A capacitor (C2) is coupled to the output of line (20) of the network (10) in parallel with the load (21) to be supplied with the regulated voltage (V2). The regulator device (18) is switched on and off in a cyclical manner to minimize its power dissipation yet reap the advantages inherent with such devices. In its on state, capacitor (C2) is supplied with sufficient charging current from the regulator device (18). When the device (18) is turned off, charging current is supplied from the second winding (N2). Provision is made for generating different regulated voltage levels (V3) by the inclusion of a third winding (N3).

Abstract: A digital processor including both macro and micro instruction generators. The micro-instruction generator comprises a sequencer for generating instruction addresses, a memory for generating instructions in response to the addresses and a pipeline register adapted to receive the instructions for execution. The sequencer operates at a constant CLK 1 rate while the pipeline register operates at a variable CLK 2 rate; i.e., the occurrence of a branch instruction in the pipeline register operates to inhibit CLK 2 for one CLK 1 time so as to prevent loading for execution of the aborted sequential instruction during the loading of a new non-sequential instruction address. CLK 2 resumes upon the next CLK 1 signal to resume sequential operation. Special branch instructions are utilized to fetch macro-instructions from a pipelined system of macro-instruction registers. A two-tier synchronous arbitration system for memory requests is also disclosed.