Patents Assigned to NO. 24 RESEARCH INSTITUTE OF CHINA ELECTRONIC TECHNOLOGY CORPORATION
  • Clock delay adjusting circuit based on edge addition and integrated chip thereof
    Patent number: 10404243
    Abstract: The invention provides a clock delay adjusting circuit based on edge addition and an integrated chip thereof.
    Type: Grant
    Filed: October 20, 2014
    Date of Patent: September 3, 2019
    Assignee: NO. 24 RESEARCH INSTITUTE OF CHINA ELECTRONIC TECHNOLOGY CORPORATION
    Inventors: Rongbin Hu, Can Zhu, Yonglu Wang, Zhengping Zhang, Lei Zhang, Yuhan Gao, Rongke Ye, Guangbing Chen, Yuxin Wang, Dongbing Fu
  • CLOCK DELAY ADJUSTING CIRCUIT BASED ON EDGE ADDITION AND INTEGRATED CHIP THEREOF
    Publication number: 20170214397
    Abstract: The invention provides a clock delay adjusting circuit based on edge addition and an integrated chip thereof.
    Type: Application
    Filed: October 20, 2014
    Publication date: July 27, 2017
    Applicant: NO. 24 RESEARCH INSTITUTE OF CHINA ELECTRONIC TECHNOLOGY CORPORATION
    Inventors: Rongbin HU, Can ZHU, Yonglu WANG, Zhengping ZHANG, Lei ZHANG, Yuhan GAO, Rongke YE, Guangbing CHEN, Yuxin WANG, Dongbing FU
  • High speed sampling front-end circuit
    Patent number: 9455735
    Abstract: A high-speed sampling front-end circuit is presented that includes a MDAC sampling network, a reference voltage generator circuit, a comparator array, an operational amplifier, an output short-circuit switch, an adjustable clock duty cycle stabilizer, a status control module and a feedback control module. The circuit features low power, high sampling rate and high input bandwidth of sampling network. The time constant of the MDAC sampling network and the comparator array is precisely matched one another to improve input bandwidth of the sampling network. Sampling capacitors are designed as feedback capacitors and DAC calculation capacitors, thereby the operational amplifier doubles feedback coefficient and features 50% bandwidth and 50% power. The cycle stabilizer is adopted to shorten sampling time and extend amplification phase to greatly improve sampling rate. One input reference voltage tends to simplify the design of the reference voltage generator circuit.
    Type: Grant
    Filed: April 15, 2013
    Date of Patent: September 27, 2016
    Assignee: NO. 24 RESEARCH INSTITUTE OF CHINA ELECTRONIC TECHNOLOGY CORPORATION
    Inventors: Ting Li, Gangyi Hu, Ruzhang Li, Yan Wang, Lu Liu, Yong Zhang, Xu Wang, Yuxin Wang, Dongbing Fu, Guangbing Chen