Abstract: An improved CMOS pixel with a combination of analog and digital readouts to provide a large pixel dynamic range without compromising low-light performance using a comparator to test the value of an accumulated charge at a series of exponentially increasing exposure times. The test is used to stop the integration of photocurrent once the accumulated analog voltage has reached a predetermined threshold. A one-bit output value of the test is read out of the pixel (digitally) at each of the exponentially increasing exposure periods. At the end of the integration period, the analog value stored on the integration capacitor is read out using conventional CMOS active pixel readout circuits.

Abstract: A semiconductor waveguide includes a section containing free charge, either electrons or holes, which can be steered into or removed from the path of the beam under the control of electrical signals. The mobile charges come from a potential well which may be either filled or depleted under electrical control. When the well is filled, the charges speed the beam propagation, introducing a phase change. When the well is emptied the beam propagates with extra delay. The phase shifter allows very high speed modulation of the beam using low voltage and low power electronics. The device can be created using standard silicon processing techniques, and integrated with other optical components such as splitters and combiners to create amplitude modulators, attenuators and other optical devices.

Abstract: A method of making a semiconductor device having a predetermined epitaxial region, such as an active region, with reduced defect density includes the steps of: (a) forming a dielectric cladding region on a major surface of a single crystal body of a first material; (b) forming a first opening that extends to a first depth into the cladding region; (c) forming a smaller second opening, within the first opening, that extends to a second depth greater than the first depth and that exposes an underlying portion of the major surface of the single crystal body; (d) epitaxially growing regions of a second semiconductor material in each of the openings and on the top of the cladding region; (e) controlling the dimensions of the second opening so that defects are confined to the epitaxial regions grown within the second opening and on top of the cladding region, a first predetermined region being located within the first opening and being essentially free of defects; (f) planarizing the top of the device to remove all