Abstract: An LC resonance element (10) includes a dielectric film (12), a common electrode (11) formed of a thin-film conductor on a lower surface (12D) of the dielectric film, a first capacitor (C1) and a second capacitor (C2) that are connected in series via the common electrode (11) and constitute a thin-film capacitor (TC), first and second external connection terminals (14A, 14B) formed on an upper surface (12U) of the dielectric film, a thin-film conductive wire (16) constituting a thin-film inductor (TL), a first upper electrode (13A) of the first capacitor formed on the upper surface (12U), and a second upper electrode (13B) of the second capacitor formed on the upper surface (12U). The thin-film conductive wire (16) is formed in a region (R2) located on the upper surface (12U) of the dielectric film and outside the common electrode (11) in plan view.

Abstract: An LC resonance element (10) includes a dielectric film (12), a common electrode (11) formed of a thin-film conductor on a lower surface (12D) of the dielectric film, a first capacitor (C1) and a second capacitor (C2) that are connected in series via the common electrode (11) and constitute a thin-film capacitor (TC), first and second external connection terminals (14A, 14B) formed on an upper surface (12U) of the dielectric film, a thin-film conductive wire (16) constituting a thin-film inductor (TL), a first upper electrode (13A) of the first capacitor formed on the upper surface (12U), and a second upper electrode (13B) of the second capacitor formed on the upper surface (12U). The thin-film conductive wire (16) is formed in a region (R2) located on the upper surface (12U) of the dielectric film and outside the common electrode (11) in plan view.

Abstract: A thin-film capacitor structure (50) is joined to an electrode pad surface (2S) of an area array integrated circuit (2) having a plurality of electrode pads (3G, 3P, 3S) arranged in an area array on the electrode pad surface (2S). The thin-film capacitor structure (50) includes a thin-film capacitor (10) including a first sheet electrode (11), a second sheet electrode (13), and a thin-film dielectric layer (12) formed between the first sheet electrode (11) and the second sheet electrode (12), a first insulating film (21), a second insulating film (22), and a plurality of through holes (30P, 30G, 30S). The plurality of through holes (30P, 30G, 30S) are bored from the first insulating film (21) to the second insulating film (22) through the thin-film capacitor (10) and formed in positions corresponding to the plurality of electrode pads (3G, 3P, 3S).

Abstract: An intermediate connector includes a power source bus bar as an elongated thin plate to be connected to each power source pad of a semiconductor integrated circuit, a ground bus bar as an elongated thin plate to be connected to each ground pad of the semiconductor integrated circuit, a thin film insulator layer formed between the power source bus bar and the ground bus bar, and a conductive path portion as an elongated thin plate including a plurality of conductive paths to be connected to each signal pad of the semiconductor integrated circuit. The power source bus bar, the ground bus bar, and the conductive path portion are arranged in parallel correspondingly to a parallel arrangement of a power source pad row, a ground pad row, and a signal pad row of the semiconductor integrated circuit.

Abstract: A circuit substrate includes: a base material; and a capacitor layer. The capacitor layer includes a first metal layer that is provided on the base material, a dielectric layer that is provided on the first metal layer, and a second metal layer that is provided on the dielectric layer. The first metal layer includes a first electrode region which is provided on the base material and is exposed from the dielectric layer and to which a first terminal of a capacitor element for supplying current to a circuit part through the capacitor layer is connected. The second metal layer includes a second electrode region in which the second metal layer is exposed and to which a second terminal of the capacitor element is connected.

Abstract: A method for manufacturing a thin-film capacitor in a circuit substrate includes: forming, on a dielectric film formed on a surface of a support member, a first electrode layer of the thin-film capacitor; forming, on the dielectric film and the first electrode layer, an insulating base material of the circuit substrate so as to bury the first electrode layer; removing the support member and exposing a surface of the dielectric film on a side opposite to the first electrode layer; patterning the dielectric film so as to leave a dielectric layer overlapping the first electrode layer; forming a first through hole in the dielectric layer so as to expose a part of a surface, on a dielectric layer side, of the first electrode layer; and forming a second electrode layer of the capacitor so as to overlap the dielectric layer including the inside of the first through hole.

Abstract: A multi-layered circuit board includes a first insulating layer, a second insulating layer, and a sheet capacitor that is located between the first insulating layer and the second insulating layer. The sheet capacitor includes a pair of electrodes that sandwich a dielectric. Lead wirings continue to the electrodes, respectively. The lead wirings are disposed on an opposite side of the first or the second insulating layer with respect to the sheet capacitor to overlap the electrodes when viewed from a stacking direction of the multi-layered circuit board. Because the lead wirings are arranged to overlap the electrodes in the stacking direction of the multi-layered circuit board, an ESL of the sheet capacitor is maintained low.

Abstract: A circuit substrate includes: a base material; and a capacitor layer. The capacitor layer includes a first metal layer that is provided on the base material, a dielectric layer that is provided on the first metal layer, and a second metal layer that is provided on the dielectric layer. The first metal layer includes a first electrode region which is provided on the base material and is exposed from the dielectric layer and to which a first terminal of a capacitor element for supplying current to a circuit part through the capacitor layer is connected. The second metal layer includes a second electrode region in which the second metal layer is exposed and to which a second terminal of the capacitor element is connected.

Abstract: A circuit substrate includes: a base material; and a capacitor layer. The capacitor layer includes a first metal layer that is provided on the base material, a dielectric layer that is provided on the first metal layer, and a second metal layer that is provided on the dielectric layer. The first metal layer includes a first electrode region which is provided on the base material and is exposed from the dielectric layer and to which a first terminal of a capacitor element for supplying current to a circuit part through the capacitor layer is connected. The second metal layer includes a second electrode region in which the second metal layer is exposed and to which a second terminal of the capacitor element is connected.

Abstract: A semiconductor device is provided with: a semiconductor integrated circuit having a bump mounting surface; and a thin-film capacitor portion connected to the bump mounting surface via a bump. The semiconductor integrated circuit includes a first power supply pad, and a second power supply pad. The thin-film capacitor portion includes a first electrode layer connected to the first power supply pad, a second electrode layer connected to the second power supply pad, and a dielectric layer formed between the first electrode layer and the second electrode layer. The semiconductor device is provided with an electric power supply path configured to supply electric power to the semiconductor integrated circuit, and a thin plate-shaped metal resistor portion provided in the electric power supply path and made from a metal based high-resistance material having a volume resistivity higher than a volume resistivity of the first electrode layer and the second electrode layer.

Abstract: A circuit substrate includes: a base material; and a capacitor layer. The capacitor layer includes a first metal layer that is provided on the base material, a dielectric layer that is provided on the first metal layer, and a second metal layer that is provided on the dielectric layer. The first metal layer includes a first electrode region which is provided on the base material and is exposed from the dielectric layer and to which a first terminal of a capacitor element for supplying current to a circuit part through the capacitor layer is connected. The second metal layer includes a second electrode region in which the second metal layer is exposed and to which a second terminal of the capacitor element is connected.

Abstract: A semiconductor device is provided with: a semiconductor chip die-bonding mounted face up on a support; an intermediate substrate connecting the semiconductor chip to a plurality of external connection portions; and a plurality of connection bumps connecting the semiconductor chip and the intermediate substrate. The plurality of connection bumps includes a plurality of power supply bumps connected to a plurality of electrode pads on the semiconductor chip for supplying power to the semiconductor chip. The intermediate substrate includes: a plurality of power supply pads connected to the plurality of electrode pads through the plurality of power supply bumps; a bump surface facing the semiconductor chip and having a plurality of power supply pads formed thereon; an external connection surface having a plurality of external connection pads formed thereon connected to the external connection portions; and a capacitor connected to the plurality of power supply bumps.

Abstract: A semiconductor memory device includes a thin-film capacitor disposed at a position facing a circuit surface of a memory chip except for a center pad region. The thin-film capacitor includes a first plane electrode, a thin-film dielectric layer, and a second plane electrode. The first plane electrode includes a first power supply input portion to which a power supply voltage of one polarity is provided, and a first power supply output portion disposed near the center pad region to output the power supply voltage of one polarity to a center pad. The second plane electrode is formed on the dielectric layer and includes a second power supply input portion to which the power supply voltage of the other polarity is provided, and a second power supply output portion disposed near the center pad region to apply the power supply voltage of the other polarity to the center pad.

Abstract: A semiconductor device is provided with: a semiconductor chip die-bonding mounted face up on a support; an intermediate substrate connecting the semiconductor chip to a plurality of external connection portions; and a plurality of connection bumps connecting the semiconductor chip and the intermediate substrate. The plurality of connection bumps includes a plurality of power supply bumps connected to a plurality of electrode pads on the semiconductor chip for supplying power to the semiconductor chip. The intermediate substrate includes: a plurality of power supply pads connected to the plurality of electrode pads through the plurality of power supply bumps; a bump surface facing the semiconductor chip and having a plurality of power supply pads formed thereon; an external connection surface having a plurality of external connection pads formed thereon connected to the external connection portions; and a capacitor connected to the plurality of power supply bumps.

Abstract: A power supply wiring structure of a semiconductor device including a semiconductor chip flip-chip mounted on a substrate decreases the characteristic impedance of internal wiring and thereby increases the noise reduction effect, while achieving low impedance during high frequency power supply operation. A semiconductor device has an inner power supply plate structure on a first insulating film on a protection film of a semiconductor chip, in an inner region of a plurality of peripheral electrode pads on a mounting surface of the semiconductor chip as viewed in plan, for supplying power to the semiconductor chip. The inner power supply plate structure includes a first power supply plate on the first insulating film, a second insulating film on the first power supply plate, and a second power supply plate on the second insulating film.

Abstract: A semiconductor device includes a semiconductor chip, an interposer, a surface circuit pattern, and a post array. The surface circuit pattern is formed on one surface of the interposer and includes chip side pads connected to an external connection pad of the semiconductor chip, junction pads, and interconnecting lines having an end connected to the chip side pads and another end connected to the junction pads. The interconnecting lines extend from the chip side pads toward an outer edge of the interposer. The post array includes conducting paths and insulating resin insulating the conductive paths from each other. The post array is arranged such that the conductive paths extend in a direction intersecting with the surface of the interposer. The conducting paths each have an end connected to the junction pad and another end to be connected to the printed wiring board.

Abstract: A semiconductor device includes a semiconductor chip, an interposer, a surface circuit pattern, and a post array. The surface circuit pattern is formed on one surface of the interposer and includes chip side pads connected to an external connection pad of the semiconductor chip, junction pads, and interconnecting lines having an end connected to the chip side pads and another end connected to the junction pads. The interconnecting lines extend from the chip side pads toward an outer edge of the interposer. The post array includes conducting paths and insulating resin insulating the conductive paths from each other. The post array is arranged such that the conductive paths extend in a direction intersecting with the surface of the interposer. The conducting paths each have an end connected to the junction pad and another end to be connected to the printed wiring board.

Abstract: A method for manufacturing a printed wiring board, including forming a thermosetting resin layer on the printed wiring board; heating and curing the resin layer; and then polishing the cured resin layer, thereby exposing the circuit patterns. Additionally, the step of heating and curing includes maintaining the resin layer at a non-curable temperature in a state where the resin layer is pressed via the smoothing plate in a reduced pressure chamber; heating the resin layer in the pressed state to a curing temperature; introducing outside air into the reduced pressure chamber with the pressed state and the curing temperature maintained; reducing the pressure applied to the smoothing plate with the curing temperature maintained; and cooling the resin layer.

Abstract: There is provided a method for manufacturing a flat printed wiring board in which spaces between circuit patterns are filled with a resin. The method comprises: laminating via a mold release film a plurality of sets of laminated bodies formed by superposing a semi-cured resin sheet on a printed wiring board with circuit patterns formed thereon; placing the laminated plural sets of the laminated bodies interposed between a pair of smoothing plates and collectively pressing the laminated bodies in a reduced pressure atmosphere used for curing the resin; and then polishing the cured resin covering the circuit patterns, thereby exposing the circuit patterns.

Abstract: A vacuum print system comprising: an outer shell to define an airtight inner space and having a closure door at a ceiling thereof; a printer provided in the airtight inner space; a worktable to supply a work to the printer provided in the airtight inner space operable to move; and an air exhaust system connected to the airtight inner space is disclosed. The worktable is operable to move between a sealing position and a work supplying position. The worktable at the sealing position divides the airtight inner space into two airtight compartments, a first compartment having the closure door, and a second compartment having the printer provided therein and the air exhaust system connected thereto. The worktable at the work supplying position supplies the work to the printer. Further, the closure door is operable to open to take the work in and out when the worktable is at the sealing position.