Abstract: An integrating circuit is formed in the present invention, of which the active element is a pair of bipolar transistors (T5/T6) or a CMOS transistor (T8) which with the aid of switches (s81 to s88) controls the storing of a sample charge from the signal voltage (Us) in a sampling capacitor (Ci) and the discharging of the sample into an integrating capacitor (Co). The circuit only consumes current while charges are being transferred.

Abstract: The power consumption of an electrical device can be optimised by altering the clock frequency of circuits (MCU, 1-3) in the device which are controlled by a clock signal. The state and need for processing power of the circuits (MCU, 1-3) or blocks (21-23) in the circuits (2) is supervised, and the clock frequency of the circuit (MCU, 1-3) or block (21-23) in the device is changed according to the need for processing power. The appropriate clock frequency is selected from one of a plurality of clock signals (clk(1) . . . clk(n)), input to a selection circuit which is then coupled to the output of the selection circuit for use as the clock for the circuit.

Abstract: Structure and technique, for calibrating a vector modulator that does not require a network analyzer, are disclosed which are incorporated in a vector modulation system comprising a standard vector modulator circuit including means for shifting phase to adjust the relative phases of the I and Q components of the modulated RF carrier. Means for attenuating are included in the I and Q modulation system to adjust the relative amplitude of the modulation signals. The disclosure describes a technique wherein the microwave transmitter's I and Q phase difference is measured by measuring the power levels of the I and the Q signals. The power levels are compared and a correction value is stored in a read-only memory to compensate for the error.

Abstract: A signal generator includes a frequency divider having an input node for receiving a first signal having a first frequency f.sub.1 and a single output node for outputting a second signal having a second frequency f.sub.2, wherein a ratio f.sub.1 /f.sub.2 is equal to an odd number that is equal to or greater than three. A synchronous delay circuit has an input node coupled to the single output node of the frequency divider and an output node for outputting a third signal that is delayed in time with respect to the second signal by an amount that is a function of a period of the first signal. Logic is provided having a first input node coupled to the single output node of the frequency divider and a second input node coupled to the output node of the delay circuit. The logic has an output node for outputting a fourth signal having the second frequency f.sub.2 and a 50% duty cycle.

Abstract: The invention relates to an EMC enclosure (4) used in radiotelephones as protection of the radiotelephone components, the enclosure (4) having no separate cover in order to service or to repair the components. Between the cover (16) and the side walls (15) the EMC enclosure has necks (7,11) with openings (8,12,13,14) between them. Due to these openings it is possible to open the cover (16) with a suitable tool. When the cover has (16) been opened it is possible to solder it back or to use a repair cover.

Abstract: The invention relates to a clip assembly for releasable attachment to a body. The assembly comprises a clip member mounted on an attachment member which is configured for insertion into a corresponding recess provided in the body. The assembly further comprises urging means which bias the clip member towards the body and also biases the attachment member into locking engagement in the recess.(FIG.

Abstract: A compact battery pack (1) for use with an electronic apparatus comprising a housing (2) having a wall portion (21) which is provided with a recess (8) to accommodate a substrate 6 having present thereon at least two electrical terminals 5 for contacting cells (4) provided in a cavity (3) within the housing. The substrate (6) is contained within the thickness of the recess (8) so that it does not extend into the cavity (3).

Abstract: Electronic apparatus generates first and second output signals having a quadrature phase relationship therebetween. A local oscillator signal with a reference phase is applied as an input to first and second signal branches. The second signal branch includes a phase control circuit for subjecting input signals passing therethrough to a determined phase shift. The phase control circuit is responsive to an applied DC control signal to adjust any phase shift error through the phase shift circuit from a predetermined phase shift to assure that the second output signal exhibits the required quadrature phase relationship to the first output signal. A memory/microprocessor combination stores a digital value that is indicative of a DC control signal which must be applied to the control circuit to alter the phase shift through the phase control circuit to the predetermined phase shift. The microprocessor accesses the digital parameter and applies it to the phase control circuit through a digital to analog converter.

Abstract: The invention relates to a biased electronic circuit in which a voltage-controlled component has a characteristic with a non-linear portion and a substantially linear portion. The circuit is biased by a voltage being applied to one terminal of the component thereby shifting the operation of the component to the linear portion.

Abstract: A data adapter (2) for a mobile telephone (1) of the type intended to have a subscriber identity module (SIM) inserted therein and capable of supporting a short message service (SMS). The adapter includes means for coupling to the telephone so that data can be transferred therebetween. The coupling means includes a connector configured as a standard SIM, i.e. designed to fit in the SIM interface (3) of the telephone (1). The adapter itself includes means (6,7) for receiving a SIM such that data can be read from or written to the SIM. Means are included in the adapter for converting received data into SMS format thereby enabling the mobile telephone to be used for receiving/transmitting data messages other than normal SMS messages. A data input/output (8) may be provided on the adapter for connection to an external data terminal, e.g. a PC.

Abstract: A deviation limiting transmission circuit comprising a soft clipper (13) which performs measurements at two nodes. The soft clipper (13) limits both its own output signal and the output signal of a low-pass/band-stop filter (8) to selected maximum values thus preventing prolonged deviation overshoots.

Abstract: A radio telephone system and method of operation thereof, wherein the power consumption of the mobile stations in the system is reduced. The system includes a base station, at least one auxiliary base station and at least one mobile station. The levels of the received signals are indicated at the base stations and their levels are compared. The one having the highest indicated level will be selected as the receiving base station. At the same time, the base station transmits the pilot message to the mobile station in order to adjust its transmission power to a suitably low level.

Abstract: The program code of an object program of a radiotelephone is recorded into a RAM (3) rather than in an EPROM as is conventional. The checking of the program code and the loading of the program from an external device coupled thereto via an external bus is controlled by program recorded in a ROM (4). This allows the program code to be changed and updated as required with time consuming and expensive replacement of a whole memory.