Abstract: In an interpolating method for interpolating interpolated data between discrete items of digital data, there are obtained values of (2.sup.n-1) number of interpolated points which divide, into 2.sup.n -number of almost equal portions, the interval between two intermediate items of data, which are among four consecutive items of data with the exception of two items of data at both ends thereof. These values are obtained from the four consecutive items of data using a bit-shift operation and an addition/subtraction operation. For example, let g(x.sub.i-1), g(x.sub.i), g(x.sub.i+1), g(x.sub.i+2) represent the data values of four, i.e., first through fourth, consecutive points x.sub.i-1, x.sub.i, x.sub.i+1, x.sub.1+2. Three interpolated points are interpolated between the two intermediate points x.sub.i, x.sub.i+1 by computing an interpolated value f(P.sub.i) at a point P.sub.i intermediate the two intermediate points x.sub.i, x.sub.i+1 in accordance with the following equation:f(P.sub.i)=[g(x.sub.i-1)+g(x.sub.

Abstract: An inverter portion, which is to be basic logic circuit, includes switching FETs corresponding to input terminals and a load FET. A logic signal inputted into each of the input terminals drives each corresponding switching FET, thereby to output a prescribed logic signal from an output terminal. Further, a load for restricting a current flowing in the load FET is connected between the gate and the source of the load FET. In addition, a load current control FET is provided for controlling the current in this load. A gate potential of the load current control FET is produced by a diode OR circuit. The diode OR circuit outputs a logic OR of the logic signals inputted into the respective input terminals, and supplies it to the gate of the load current control FET as a load current control signal.