Abstract: A method of forming isolation trenches in CMOS integrated circuits is disclosed. The trench side walls are covered by a thin oxide layer, and the trenches are filled with a highly doped polysilicon. The doped polysilicon has a high work function which prevents oxide charges from inverting the trench side walls and thereby turns off the parasitic transistors at these side walls to reduce latchup.

Abstract: The tail current of a differential transistor pair (12 and 14) is controlled by a feed-back means (40) that couples the pair's tail node (16) to the control input of each transistor for controlling a biasing current through each transistor. The control input of each transistor further receives an input signal in addition to an output signal of the feed-back means. As a result, the circuit has a stable and accurate tail current, and in addition is suitable for a low-voltage supply or for high-current operation.

Abstract: A planar electrical interconnection system suitable for an integrated circuit is created by a process in which an insulating layer (31) having a planar upper surface is formed on a substructure after which openings (32) are etched through the insulating layer. A conductive planarizing layer (33) having a planar upper surface is formed on the insulating layer and in the openings by an operation involving isotropic deposition of a material, preferably tungsten, to create at least a portion of the planarizing layer extending from its upper surface partway into the openings. The planarizing layer is then etched down to the insulating layer. Consequently, its upper surface is coplanar with that of the material (33') in the openings. The foregoing steps are repeated to create another coplanar conductive/insulating layer (34 and 36'). If the lower openings are vias while the upper openings are grooves, the result is a planar interconnect level. Further planar interconnect levels can be formed in the same way.

Abstract: In hermetically sealing a base structure (10) of a ceramic package for a semiconductor device to a cap structure (12) of the device, one or more venting slots (36) are initially provided in the base sealing layer (16) or in the cap sealing layer (26). The base and cap structures are then fused together along the two sealing layers and electrical leads (20) by bringing the structures into contact and heating them to a temperature high enough to cause the sealing material to flow readily. The venting slots allow air to escape during the fusing step. This inhibits the formation of air bubbles along the sealing interface and thereby improves the hermeticity of the seal. The structures are subsequently cooled to harden the sealing layers into a unitary layer (28).

Abstract: A method of fabricating a CMOS-type structure entails forming a pair of conductive portions (68 and 70) on a pair of dielectric portions (72 and 74) lying on monocrystalline silicon (60). N-type dopant-containing ions are implanted into the silicon to form a pair of doped regions (78/82) separated by p-type material under one of the dielectric portions. Boron dopant-containing ions are similarly implanted to form a pair of doped regions (84) separated by n-type material under the other dielectric portion. A sacrificial oxidation is performed by oxidizing surface material of each conductive portion and each doped region and then removing at least part of the so oxidized material (86) down to the underlying silicon. Tungsten (88 and 90) is deposited on the exposed silicon after which a patterned electrical conductor is provided over the tungsten. Use of the sacrificial oxidation substantially reduces tunnel formation during the tungsten deposition.

Abstract: The size of a fusible link (22C.sub.F) created from part of a metal layer (22) is controlled by an oxidation performed in a deposition chamber that is also used for depositing a dielectric layer (30) over the fuse structure. The metal layer serves as a diffusion barrier between semiconductor material (14 and 16) and another metal layer (24).

Abstract: In a transistor fabrication process, the use of a three-step base doping technique enables the characteristics of a vertical bipolar transistor to be controllably reproduced at highly optimal values from run to run. Insulating spacers (52A) are employed in forming a self-aligned base contact zone (58B). A shallow emitter (46) is created by outdiffusion from a patterned non-monocrystalline semiconductor layer (38A) that serves as the emitter contact. The fabrication process is compatible with the largely simultaneous manufacture of an insulated-gate field-effect transistor of the lightly doped drain type.

Abstract: Aluminum alloy polycrystalline conductors having reduced electro-migration tendencies are formed in a semiconductor device by applying a thin film of aluminum or aluminum alloy to an array of shallow holes provided in a dielectric layer the array being patterned according to a desired interconnection pattern. A thin film of aluminum or aluminum alloy is then scanned with a laser beam sufficient to melt the film and cause it to planarize. An oriented crystal structure is formed with grain boundaries being aligned orthogonally to the rows and column of the hole pattern. A photoresist mask is then aligned with the resultant crystal structure in a manner such that boundaries extend substantially only in a direction across the width of the desired conductor lines. The aluminum which is present in the crystal structure outside the desired conductor line is then removed by plasma etching through the mask.

Abstract: A Schottky-type diode is fabricated by a process that enables the diodes conductor-to-semiconductor barrier height .phi..sub.B to be controlled by adjusting the thickness of a metal silicide layer (22) which forms a rectifying junction (20) with an N-type semiconductor (24). In fabricating one version of the diode, a metallic layer (70) consisting of two or more metals such as platinum and nickel is deposited on an N-type silicon semiconductor (68) and heated to create a metal silicide layer (72) consisting of a lower layer (62) and an upper layer (74) of different average composition. A portion of the upper layer is then removed, allowing .phi..sub.B to be adjusted suitably.

Abstract: A field-programmable device contains a buffer (20) located between a pair of programmable circuits (14 and 16) along a column (10) connecting the circuits. The buffer provides increased current to the column portion connected to one of the circuits (16) without increasing the current supply requirements for the column portion connected to the other circuit (14). This permits the device to switch faster and/or to accommodate programmable circuits of large size. The buffer also enables the same select circuitry to be used in programming both circuits without causing a significant voltage between them during normal operation.