Abstract: In a memory element comprising interconnected logic gates with field effect transistors metastable states are to be avoided. The device's immunity against staying in metastable states is considerably raised by coupling a supply terminal of each logic gate to a power supply voltage via a base-emitter path of a bipolar transistor that has its collector coupled to the logic gate's output.

Abstract: An electronic circuit contains a main stage (10 and 12) that produces a digital code consisting of a plurality of bits (B.sub.1 -B.sub.M-1) that make binary transitions as a function of an input parameter (V.sub.I). A synchronization stage (14 and 16) synchronizes transitions of bits (B.sub.0 -B.sub.K-1) in one part of the code with corresponding transitions of bits (B.sub.K -B.sub.M-1) in another part. When the input parameter is in transition regions where bits in the first-mentioned part of the code could go to wrong values, the synchronization stage suitably replaces the values of bits in the first part with information based on bits in the other part.

Abstract: A semiconductor PROM contains a group of PROM cells (12) each consisting of a pair of opposing diodes oriented vertically with their common intermediate region (22) fully adjoining a recessed oxide insulating region (16). A composite buried layer consisting of buried regions (32) which adjoin the insulating region below the lower cell regions (20) and an opposite-conductivity buried web (44) which laterally surrounds each buried region is employed to improve programming efficiency. Connective regions (46) extend from the buried web to the upper semiconductor surface to contact electrical leads (54) typically arranged in a parallel pattern. The maximum dopant concentration in the intermediate cell regions occurs vertically within 20% of their mid-points.

Abstract: A differential amplifier coupled between sources of a high supply voltage (V.sub.HH) and a low supply voltage (V.sub.LL) contains a pair of differential portions (30 and 32) that are used to amplify a differential input signal (V.sub.11 and V.sub.12). One of the differential portions is turned on when the common-mode voltage of the input signal is in a portion of the supply range extending up to the high supply voltage. The other is turned on when the input common-mode voltage is in a portion of the supply range extending down to the low supply voltage. A level-shift circuit (38, 40, 42, 44, and 46) selectively raises or loweres the voltages at input points (P1, P2, P3, and P4) to the differential portions. The level shifts extend the conductive ranges of the differential portions. This enables the amplifier to achieve rail-to-rail input capability down to 1 volt or slightly less for the power supply voltage.

Abstract: Page-mode-organized ROMs and associated circuitry are connected only to data and control buses in an information processing system. Addressing and reading of the ROMs are controlled by a processor without connecting the ROMs to an address bus. Selection of a particular ROM and of a particular page in the selected ROM is accomplished by applying a first control signal to the control bus and a first data word to the data bus. This first data word thus serves as the address of the selected page in the selected ROM. Then a particular byte of the selected page is selected by applying a second control signal to the control bus and a second data word to the data bus. This second data word serves as the address of the selected byte. Subsequently, in response to a third control signal, the selected byte is read out of the selected ROM and applied to the data bus.

Abstract: The invention centers around a system for interpolating between multiple pairs of complementary main signals to generate further pairs of complementary signals. An input circuit (10) supplies the main signals. The interpolation is a two-step operation. The first step is done with two strings (S and S.sub.N) of impedance elements (R.sub.0 -R.sub.N-1 and R.sub.N0 -R.sub.NN-1). Each pair of main signals is supplied to a corresponding pair of nodes along the strings. Interpolated signals are taken from other pairs of corresponding nodes along the strings. In the second interpolation stage, a delay network (D) formed with additional impedance elements (R.sub.D0 -R.sub.DN-1 and R.sub.DN0 -R.sub.DNN-1) compensates for transmission delays through the impedance elements that make up the strings.

Abstract: An edge-sensitive dynamic switch center around a transmission gate (16) formed with a pair of complementary FET's (Q.sub.N and Q.sub.P) coupled together in parallel between a pair of nodes (1 and 2). The signals at the two nodes vary between a low voltage level and a high voltage level. An inverter (17) is coupled between the gate electrodes of the FET's. A delay element (18) is coupled between one of the nodes and one of the gate electrodes. Due to the transmission delays through the delay element and the inverter, the switch turns off with a controlled delay.

Abstract: An error correction circuit employs a digital averaging technique to overcome transition bit errors in a plurality of original binary bits ideally arranged as a thermometer or circular code. The circuit first generates a like plurality of intermediate signals respectively corresponding to the original bits. Each intermediate signal varies according to a weighted analog summation of a specified odd number of consecutive original bits centered about the corresponding bit. The circuit then compares the intermediate signals with corresponding further signals to produce a corrected code.

Abstract: A TTL compatible buffer circuit responsive to an input signal and having a controlled ramp output is disclosed and includes a low and a high output voltage driver, each driver being comprised of a Darlington pair of transistors, and each driver being separately controlled by its own control circuit. Each control circuit includes at least a capacitor and resistor which are arranged to control the voltage at the base of the upper transistor of the Darlington pair output voltage driver. In this manner, the voltage at the high voltage driver increases in a substantially linear manner when the input signal goes from low to high, and the voltage at the low voltage driver decreases in a substantially linear manner when the input signal goes from high to low. The turn on time of the drivers is thus relatively long. Each control circuit further includes a transistor which permits the respective output voltage driver to turn off quickly.

Abstract: A highly accurate current-limiting circuit prevents an output current (I.sub.OUT) flowing through an output line (L.sub.OUT) from exceeding a specified value (I.sub.LIM) of an input current (I.sub.IN) flowing through an input line (L.sub.IN). The circuit contains a first channel device (10) controlled by a first reference voltage (V.sub.REF1), a current source (12) that supplies a reference current (I.sub.REF), a second channel device (14) controlled by a second reference voltage (V.sub.REF2), a current bypass device (16), and a bypass control system (18). The current gain below the specified value of the input current is close to one. By suitably choosing certain of the circuit parameters, the circuit operates in a substantially temperature-independent manner.

Abstract: An ECL circuit (30.sub.1) formed with a pair of emmitter-coupled bipolar transistors (Q1.sub.A and Q1.sub.B), a main current source (26), a resistor (R1.sub.A), and an output transistor (Q2) contains a switching stage (38) for placing the circuit in the three-state mode when the circuit is operated in the normal ECL output voltage range. The switching stage causes current exceeding that supplied by the current source to flow through the resistor. The output transistor turns off, enabling the circuit to exhibit high output impedance.

Abstract: A glitchless terminal count indication digital counter having a clock signal as an input thereto is disclosed and comprises a state logic means comprised of a plurality of DQ flip-flops for providing a digital count with the clock signal being sent to an input thereof, a next state decode means, a next terminal count decode means for providing an indication at its output that the digital output count will reach a terminal count at the next clock cycle, and a terminal count logic means for obtaining the indication from the next terminal count decode means and providing therefrom at the next clock cycle a glitchless terminal count indication. The next state decode means has inputs and outputs, with the digital count being an input thereto, and the state logic means and the next terminal count decode means being coupled to the output thereof.

Abstract: The invention centers around a system for interpolating between multiple pairs of main complementary signals to generate further pairs of complementary signals. An input circuit (10) supplies the main signals. The interpolation is done with two strings (12) of a selected number of impedance elements (R.sub.0 -R.sub.N-1 and R.sub.NO -R.sub.NN-1). Each pair of main signals is supplied to a corresponding pair of nodes along the strings. The interpolated signals are taken from other pairs of corresponding nodes along the strings. The interpolation system is particularly suitable for use in an analog-to-digital converter of the folding type.

Abstract: A voltage translator containing a bipolar transistor (Q1), a rectifier (10), a resistor (R1), and a first clamp (12) converts an input voltage (V.sub.I) into one or more output voltages of restricted voltage swing. The first clamp clamps the emitter voltage of the transistor when it is turned on. In one version, the translator includes a second clamp (14) that clamps the collector voltage of the translator when it is turned off. The translator then provides an output voltage (V.sub.O) inverse to the input voltage. In another version, the first clamp is connected between a voltage supply (V.sub.EE) and the emitter of the transistor. Its collector is connected directly to another voltage supply (V.sub.CC) so that the translator only makes non-inverting translations.

Abstract: A self-aligned metallization for an MOS device is described in which a first layer of tungsten is selectively deposited on the exposed silicon surfaces of the device including at least the source, drain and gate regions of the device, a layer of material providing nucleation sites for tungsten is selectively formed across insulating oxide regions of the device, and a second tungsten layer is selectively deposited on the nucleating layer and the exposed first tungsten layer to provide interconnection across the oxide regions. In addition to having a low electrical resistivity, such a metallization enables relaxed mask alignment and etching tolerance requirements, and is therefore useful in VLSI circuits.

Abstract: A Schottky-type diode has a conductor-to-semiconductor barrier height .phi..sub.B that is controlled by adjusting the thickness of a metal silicide layer (22) which forms a rectifying junction (20) with an N-type semiconductor (24). The silicide layer is constituted with two or more metals such as platinum and nickel.

Abstract: Various voltage and current sources which are substantially independent of the positive supply rail are provided, some of which are also temperature independent.

Abstract: A signal-conditioning circuit provides an output signal (V.sub.O) at a frequency representative of an effect such as strain or temperature that acts on a resistance bridge (20) preferably arranged in a Wheatstone configuration. A pair of energizing voltages (V.sub.E1 and V.sub.E2) are supplied on corresponding lines (21 and 22) to energize the bridge. The signal-conditioning circuit contains an integrator (34 and C1), a comparator that compares the integrator output voltage (V.sub.I) with one of the energizing voltages (V.sub.E2), and switching circuitry (23 and 24) that suitably switches the polarity of the energizing voltages in response to the output voltage.

Abstract: An MOS device having a planar configuration in which the top surfaces of the source, drain and gate electrodes are coplanar, and the overlying electrical contact structure is also planar, is produced by a method of fabrication in which the gate is defined by forming an oxide mesa on a substrate, building up the substrate with semiconductor material around the mesa, removing the mesa, and filling the resultant trough with doped polysilicon to form the self-aligned gate. Line width and alignment control are enchanced. The planarity of the device and the improved dimensional control enable a reduction of device dimensions and consequently increased device density in integrated circuits.

Abstract: Surface features of a semiconductor structure above a predetermined level are exposed for selective treatment (e.g., etching) by forming a layer of a solvent-expanded polymer on the surface of the structure, and allowing the layer to dry and cure, thereby relaxing to the predetermined level, at which it protects the underlying structure during treatment. Subsequently, the protective layer is removed by rinsing in a solvent.