Abstract: A high voltage silicon carbide MESFET includes an electric field equalizing region in a monocrystalline silicon carbide substrate at a face thereof, which extends between the drain and gate of the MESFET and between the source and gate of the MESFET. The region equalizes the electric field between the drain and gate and between the source and gate to thereby increase the breakdown voltage of the silicon carbide MESFET. The first and second electric field equalizing regions are preferably amorphous silicon carbide regions in the monocrystalline silicon carbide substrate. The amorphous regions are preferably formed by performing a shallow ion implantation of electrically inactive ions such as argon, using the source and drain electrodes and the metal gate as a mask, at a sufficient dose and energy to amorphize the substrate face. A third amorphous silicon carbide region may be formed at the face, adjacent and surrounding the MESFET to provide edge termination and isolation of the MESFET.

Abstract: An integrated circuit power device includes many cell blocks which are electrically connected in parallel, with each of the cell blocks including at least one cell such as a MOSFET, electrically connected in parallel. A transient responsive current limiting means, such as a resistor/capacitor circuit, is electrically connected to each cell block, so that the leakage current into defective cell blocks is maintained below a predetermined level without limiting the operating speed of the device. An operable integrated circuit power device is thereby obtained, notwithstanding a defective cell block. The circuit resistors are preferably formed using the same mask and material as the gate. The circuit capacitors and common gate electrode are preferably formed using the same mask and material as the source electrode. The use of common materials eliminates the need for extra fabrication steps.

Abstract: An inverted integrated heterostructure includes an optical emission heterostructure formed of Group II-VI compound semiconductor materials having first and second opposing faces and including a layer of p-type zinc selenide or an alloy thereof at the first face. A zinc mercury selenide or a zinc telluride selenide layer is formed on the layer of p-type zinc selenide or an alloy thereof, and a mercury selenide layer is formed on the zinc mercury selenide or zinc telluride selenide layer, opposite the optical emission heterostructure. An ohmic electrode is formed on the mercury selenide layer opposite the zinc mercury selenide or a zinc telluride selenide layer, and a transparent ohmic electrode is formed on the second face of the optical emission heterostructure for allowing optical emissions from the optical emission heterostructure to pass therethrough.

Abstract: A silicon carbide field effect transistor of the present invention includes a base and source region each formed by a series of amorphizing, implanting and recrystallizing steps. Moreover, the drain, base and source regions extend to a face of a monocrystalline silicon carbide substrate and the source and base regions comprise substantially monocrystalline silicon carbide formed from recrystallized amorphous silicon carbide, The source and base regions also have vertical sidewalls defining the p-n junction between the source/base and base/drain regions, respectively. The vertical orientation of the sidewalls arises from the respective implantation of electrically inactive ions into the substrate during the amorphizing steps for forming the base region in the drain and for forming the source region in the base region. The electrically inactive ions are selected from the group consisting of silicon, hydrogen, neon, helium, carbon and argon.

Abstract: Doped silicon-germanium alloy is selectively deposited on a semiconductor substrate, and the semiconductor substrate is then heated to diffuse at least some of the dopant from the silicon-germanium alloy into the semiconductor substrate to form a doped region at the face of the semiconductor substrate. The doped silicon-germanium alloy acts as a diffusion source for the dopant, so that shallow doped, regions may be formed at the face of the semiconductor substrate without ion implantation. A high performance contact to the doped region is also provided by forming a metal layer on the doped silicon-germanium alloy layer and heating to react at least part of the silicon-germanium alloy layer with at least part of the metal layer to form a layer of germanosilicide alloy over the doped regions. The method of the present invention is particularly suitable for forming shallow source and drain regions for a field effect transistor, and self-aligned source and drain contacts therefor.

Abstract: A silicon carbide field effect transfer of the present invention includes a base and source region each formed by a series of amorphizing, implanting and recrystallizing steps. Moreover, the drain, base and source regions extend to a face of a monocrystalline silicon carbide substrate and the source and base regions comprise substantially monocrystalline silicon carbide formed from recrystallized amorphous silicon carbide. The source and base regions also have vertical sidewalls defining the p-n junction between the source/base and base/drain regions, respectively. The vertical orientation of the sidewalls arises from the respective implantation of electrically inactive ions into the substrate during the amorphizing steps for forming the base region in the drain and for forming the source region in the base region. The electrically inactive ions are selected from the group consisting of silicon, hydrogen, neon, helium, carbon and argon.

Abstract: A silicon carbide field effect device includes vertically stacked silicon carbide regions of first conductivity type, extending from a lowermost drain region to an uppermost source region. In between the drain and source regions, a drift region and a channel region are provided. The drift region extends adjacent the drain region and the channel region extends between the drift region and the source region. Control of majority carrier conduction between the source and drain regions is provided by a plurality of trenches, which extend through the source and channel region, and conductive gate electrodes therein. To provide high blocking voltage capability and low on-state resistance, the doping concentration in the drift region is selected to be greater than the doping concentration of the channel region but below the doping concentration of the drain and source regions.

Abstract: A method for forming a p-n junction in silicon carbide includes the steps of amorphizing a portion of a monocrystalline silicon carbide substrate, implanting dopant ions into the amorphous portion of the substrate and then recrystallizing the amorphous portion to thereby form a substantially monocrystalline region including the dopant ions. In particular, the amorphizing step includes the steps of masking an area on the face of the monocrystalline silicon carbide substrate and then directing electrically inactive ions to the masked area so that an amorphous region in the substrate is formed. Accordingly, the amorphous region has sidewalls extending to the face that are substantially orthogonal to the bottom edge of the amorphous region. Once the amorphized region is defined, electrically active dopant ions are implanted into the amorphous region. The dopant ions are then diffused into the amorphous region and become uniformly distributed.

Abstract: An emitter switched thyristor with buried dielectric layer includes a contiguous P-N-P-N series of semiconductor regions between an anode contact and cathode contact. These regions correspond to an anode region of second conductivity type, a first base region of first conductivity type, a second base region of second conductivity type on the first base region, and a floating emitter region contacting the second base region and forming a P-N junction therewith. In addition, a field effect transistor is also provided between the cathode contact and the floating emitter for controlling turn-on and turn-off. An insulating region is also provided between the cathode region and the second base region and prevents the formation of a parasitic thyristor between the cathode contact and the anode contact. The insulating region preferably includes a buried dielectric layer selected from the group consisting of SiO.sub.2, Si.sub.3 N.sub.4, Al.sub.2 O.sub.3 and MgAl.sub.2 O.sub.4.

Abstract: An integrated multicelled thyristor includes a plurality of main thyristor cells and a plurality of edge thyristor cells. The main thyristor cells comprise source cells located in the center or innermost portion of an integrated thyristor and the edge cells are located at the periphery. In order to insure that all thyristor cells turn off uniformly, current exporting means is provided from the source cells to the edge cells to reduce current hole crowding in the peripheral cells. The anodes of all cells are electrically connected and the cathodes of all main cells are electrically connected. However, the cathodes of the edge cells are electrically connected to one or more source cells by the current exporting means. The unit cell of the multicelled device preferably comprises a BRT, but can comprise other well known thyristor structures where turn-off is limited by hole-current crowding.

Abstract: An emitter switched thyristor with base resistance control for preventing parasitic latch-up includes a P-N-P-N main thyristor with an N.sup.+ floating emitter for MOS-gated controlled turn-on and a lateral P-channel MOSFET for shunting hole current in a second base region to a P.sup.+ diverting region electrically connected to the cathode. The P-channel MOSFET is enabled by the application of a negative gate voltage to form a P-type inversion layer between the second base region and the P.sup.+ diverter region, thus reducing the resistance between the cathode and the second base region and raising the holding current of the emitter switched thyristor to above the operating current level. The formation of an alternative current path to the cathode has the further effect of reducing the forward bias across the base-emitter junction of an adjacent parasitic thyristor to thereby prevent the sustained regenerative action of the parasitic thyristor.

Abstract: An emitter switched thyristor without parasitic thyristor latch-up susceptibility includes a thyristor having an anode region, a first base region, a second base region in the first base region and an emitter region of first conductivity type in the second base region. An electrical connection is provided between the emitter region and the cathode contact by a field effect transistor in the first base region. The transistor is positioned adjacent the second base region and includes a source electrically connected to the emitter region by a metal strap on the surface of the substrate. The drain of the transistor is electrically connected to the cathode contact and has a conductivity type opposite the conductivity type of the first base region. Accordingly, the cathode contact and anode contact are not separated by a four layer parasitic thyristor. Parasitic latch-up operation is thereby eliminated.

Abstract: A method for forming an oxide-filled trench in silicon carbide includes the steps of amorphizing a portion of a monocrystalline silicon carbide substrate to thereby define an amorphous silicon carbide region in the substrate and then oxidizing the amorphous region to thereby form an oxide-filled trench in the substrate. Because of the enhanced rate of oxidation in the amorphous region as compared to the rate of oxidation of the surrounding monocrystalline silicon carbide regions at relatively low temperatures, the oxide-filled trench is generally defined by the lateral and vertical dimensions of the amorphous silicon carbide region. The amorphizing step includes the steps of masking an area on the face on the monocrystalline silicon carbide substrate to thereby expose a portion of the substrate wherein the amorphous region is to be formed and then directing ions to the face, such that the ions implant into the exposed portion of the substrate and create an amorphous silicon carbide region therein.

Abstract: A Schottky barrier rectifier includes regions of different Schottky barrier heights. Preferably, alternating regions of relatively high and relative low barrier heights are provided on a semiconductor substrate and are electrically connected in parallel to form a single Schottky barrier rectifier. The alternating regions may be provided by laterally spaced apart regions of a first metal on the semiconductor substrate and a layer of a second metal on the regions of the first metal and on the semiconductor substrate between the regions of first metal. Alternatively, a plurality of spaced apart barrier altering regions, such as a plurality of shallow implants, are formed in the semiconductor substrate, and a continuous metal layer is formed on the semiconductor substrate. In yet another embodiment, plurality of laterally spaced apart trenches are formed in the semiconductor substrate.

Abstract: Doped silicon-germanium alloy is selectively deposited on a semiconductor substrate, and the semiconductor substrate is then heated to diffuse at least some of the dopant from the silicon-germanium alloy into the semiconductor substrate to form a doped region at the face of the semiconductor substrate. The doped silicon-germanium alloy acts as a diffusion source for the dopant, so that shallow doped, regions may be formed at the face of the semiconductor substrate without ion implantation. A high performance contact to the doped region is also provided by forming a metal layer on the doped silicon-germanium alloy layer and heating to react at least part of the silicon-germanium alloy layer with at least part of the metal layer to form a layer of germanosilicide alloy over the doped regions. The method of the present invention is particularly suitable for forming shallow source and drain regions for a field effect transistor, and self-aligned source and drain contacts therefor.

Abstract: A merged P-I-N/Schottky power rectifier includes trenches, and P-N junctions along the walls of the trenches and along the bottoms of the trenches. By forming the P-N junctions along the trench walls, the total area of the P-N junctions relative to the surface area of the device can be increased, to thereby improve the device's on-state characteristics without sacrificing the total area of the Schottky region. The trenches may be U or V shaped in transverse cross-section or of other transverse cross-sectional shape, and the trenches may be polygonal or circular in top view.

Abstract: A base resistance controlled thyristor with integrated single-polarity gate control includes a thyristor having an anode region, a first base region, a second base region on the first base region and a cathode region contacting the second base region and defining a P-N junction therewith. For providing gated turn-off control, a depletion-mode field effect transistor is provided on the second base region and is separated therefrom by an insulating region. In particular, an insulating region, such as a buried dielectric layer, is provided on the second base region and the depletion-mode field effect transistor is formed thereon. The depletion-mode field effect transistor is electrically connected between the cathode contact and the second base region and provides a direct electrical connection therebetween in response to a turn-off bias signal which is preferably a zero or near zero bias.

Abstract: A silicon carbide power MOSFET device includes a first silicon carbide layer, epitaxially formed on the silicon carbide substrate of opposite conductivity type. A second silicon carbide layer of the same conductivity type as the substrate is formed on the first silicon carbide layer. A power field effect transistor is formed in the device region of the substrate and in the first and second silicon carbide layers thereover. At least one termination trench is formed in the termination region of the silicon carbide substrate, extending through the first and second silicon carbide layers thereover. The termination trench defines one or more isolated mesas in the termination region which act as floating field rings. The termination trenches are preferably insulator lined and filled with conductive material to form floating field plates. The outermost trench may be a deep trench which extends through the first and second silicon carbide layers and through the drift region of the silicon carbide substrate.

Abstract: A data signal may be sampled at high speed using a clock signal by propagating the data signal and the clock signal through a series of data and clock delay elements, respectively, and latching the corresponding delayed data and clock signals. The sampling speed is thereby controlled by the relative skew between the clock and data signals, which can be made relatively small and may be limited only by noise and random variations in fabrication. Accordingly, high speed sampling may be obtained.

Abstract: The gate voltage breakdown of an integrated circuit field effect transistor, especially a compound semiconductor metal semiconductor field effect transistor (MESFET) and high electron mobility transistor (HEMT) is dramatically increased by forming an electron trap layer on the surface of the device, under the gate contact and extending beyond the gate contact towards the drain contact. The electron trap layer is preferably a high resisitivity lattice matched monocrystalline layer having at least 10.sup.18 traps per cubic centimeter. For gallium arsenide based transistors, the electron trap layer is preferably formed by low temperature molecular beam epitaxy (MBE) of gallium and arsenic fluxes, to produce a monocrystalline gallium arsenide layer having 1% excess arsenic. For indium phosphide based transistors, the electron trap layer is preferably formed by low temperature MBE of aluminum, indium and arsenic fluxes to produce a monocrystalline aluminum indium arsenide layer having 1% excess arsenic.