Abstract: A digital data processing arrangement for providing automatic substitution of a spare memory module for a malfunctioning portion of the system memory is disclosed. The substitution takes place in a manner transparent to the software programs being run in the processing system. The system memory is organized as a plurality of memory modules, each having an identical number of individually addressable words. A particular module is enabled on receipt of an appropriate signal via a dedicated lead from the system processor unit, while a particular word within that module is specified by an address received via an address bus running to address decoder units at all modules. When the error detection and identification routines of the system processor determine that a particular module is malfunctioning, a hardware register and accompanying comparison logic are arranged such that a spare module is accessed whenever the particular malfunctioning module is subsequently addressed.

Abstract: In an encoder portion, a communication system converts analog signals, into linear delta modulated (hereafter LDM) signals and LDM signals into compressed pulse code modulated (hereafter CPCM) signals while in a decoder portion, the system reconstructs the CPCM signals into LDM signals and then analog signals substantially corresponding to those originally input into the system.

Abstract: A water-proof air-pressure equalizing valve for an enclosure capable of being pressurized to match a wide range of ambient air pressures including that corresponding to the pressure of several feet of water when totally submerged, such as the instrument housing of a military-type field telephone set, comprises a sandwich structure having a thin air-permeable hydrophobic membrane clamped between two rigid perforated sheets providing mechanical support against deformation due to water or air pressure.

Abstract: After marker functions have been performed to set up a network path during normal call processing, a continuity word is inserted into the path. The output of the path is coupled back to the input via a test multiplexer at the input to circulate the continuity word. A word is taken from the path being tested after circulation and is compared to the original continuity word, with identity of comparison being verification of continuity. Continuity test apparatus includes a continuity word register and a comparator. The comparator has inputs from the continuity word register and from the network output for the path being tested. The continuity word may be inserted in the path from an output access memory for maintenance and test words, having its output to the same multiplex lead as the output buffer memory.

Abstract: An arrangement for preventing false reseizures of loop-signaling, repeat coil-coupled interoffice trunk circuits for telephone switching systems is disclosed. In the prior art, false reseizures of an incoming trunk circuit can be caused by discharge of the midpoint capacitor at the facility side of the repeat coil bridge of an associated outgoing trunk circuit at the opposite terminus of the interoffice trunk facility. During the talk state, this midpoint capacitor is charged approximately to the signaling battery supply level with polarity such that, upon termination of the talk state and accompanying tip-ring reversal, the capacitive discharge is sufficient to re-operate the supervisory relay in the distant office incoming trunk circuit, thereby generating a false reseizure attempt.

Abstract: An electronic hybrid circuit for coupling a two-wire communication path with a four-wire communication path is disclosed wherein the use of transformer coupling is eliminated. The hybrid features a novel arrangement whereby the unbalanced four-wire path incoming voice signal is amplified, then converted to a pair of balanced signal components by complementary signal injection devices coupled to opposite sides of the two-wire path. Each resultant balanced component is injected in series with a DC battery feed potential via current amplifiers in each signal injection means. Balanced two-wire path output signals are converted for transmission to the outgoing portion of the four-wire path by coupling the two-wire path to the series combination of a differential amplifier and an output buffer amplifier.

Abstract: In the T1 PCM carrier system there are 193 bits per frame, 192 of which are used for the channels. The D1 channel bank uses the 193rd bit to identify the division between frames, with a pattern from frame to frame of . . . 010101 . . . . The D2 channel bank uses the 193rd bit of alternate frames, or every 386th bit for framing. Both D1 and D2 have a framing circuit to identify the framing bit by the pattern with a normal mode and a search mode. There is a violation monitor for comparing the pattern of framing bits from frame to frame and indicating a violation if there is a deviation. In the normal mode only the framing bits are examined, and some error tolerance is allowed. Violations are registered in a memory device to check if a preset threshold is exceeded. When the threshold is exceeded, a misframe is declared, and the circuit goes into a search mode to examine other bit positions for the framing pattern. No error tolerance is allowed in the search mode.

Abstract: A system for elapsed-time calculation is disclosed. The system employs a magnetic-striped card in conjunction with a stand-alone terminal for recording the coming and going of employees, along with other pertinent payroll data, directly on the magnetic strip. The elapsed-time calculation is cumulative, thereby allowing an employee to maintain a flexible work schedule and to receive credit for all time worked during a given pay period. The system features visual feedback to the employee whenever his card is used, so as to inform him of both the total time he has accumulated over the pay period and elapsed time for the most recent period worked. Further features include the elimination of large-scale terminal and/or remote computer memory, hard-copy back-up in case of system failure, and recyclable time cards.

Abstract: A regulated voltage converter utilizing an improved method of pulse width modulation is disclosed wherein acceptable current balance and limiting in the converter switching elements are speedily achieved within one half cycle of converter operation. Converter output current is monitored, shaped according to a non-linear transfer function, and integrated to form a voltage signal for comparison with a predetermined reference level. When the integrated signal exceeds the reference level, a control signal is generated to terminate the current pulse in the inverter section of the converter. The inherent balancing and limiting characteristics of this arrangement are easily extended to applications wherein multiple converter stages are paralleled to supply higher power to a common load.

Abstract: A thyristor controlled ferroresonant voltage regulator in which the output voltage is made adjustable by varying the reset flux level of each of two parallel magnetic core paths upon which the load windings are wound. Decoupling from the alternating current source is provided by a separate inductor. The two core paths are decoupled by magnetic shunts, which provides an inductance which may be designed to obtain a soft commutation characteristic for the ferroresonant capacitor. During one half cycle of the output waveform one thyristor is enabled by an associated control circuit to complete a circuit path for the resonant capacitor through a winding on the second magnetic core path, while the flux in the first magnetic core path is clamped; in the second half cycle, another thyristor is enabled at a time determined by the control circuit, to complete a circuit path for the capacitor through a winding on the first magnetic core path while the flux in the second magnetic core path is clamped.

Abstract: A transformer-coupled power switching device control arrangement utilizes an active feedback energy source connected to the primary of the coupling transformer to enhance the turn-off drive to the power switching device. The active feedback energy source produces an output directly dependent upon the magnitude of the power switching device output current and independent of the duration of said output current. When the output current drops to zero, the active feedback source is disabled, and a bias network is connected to the transformer primary. The bias network maintains a reverse voltage at the control electrode of the power switching device and establishes a bias current through the primary suitable for resetting the transformer core flux.

Abstract: A transformer-coupled transistor base drive circuit is disclosed wherein the transformer primary control circuit includes a switching transistor, a bias supply, and a RC biasing network arrangement. The biasing arrangement is designed to ensure that the transformer core will never enter the positive saturation region of its hysteresis characteristic; regardless of variations in the power transistor duty cycle. The base drive circuit also features provision of high sweep-out current in the power transistor base during turn-off, reverse base-emitter voltage during the power transistor off state, and regenerative current drive to minimize storage time and to control the bias power drain.

Abstract: A telephone central office switching system with economical application to small community dial office sizes is disclosed. Communication paths are spatially switched over a modular network fabric comprised of electromechanically actuated metallic crosspoints. A distributed control concept is employed wherein the logic power and flexibility of electronic stored program control is spread over many points in the system. Serial asynchronous messages between any two control elements are routed via a central information exchange unit whose number of communication ports is easily changed on a pluggable basis. Modularity is emphasized throughout the switching system for facile growth and additions of feature-oriented service packages.

Abstract: A telephone central office switching system including a non-symmetric four stage (ABC+D) folded network and junctor circuits whereby a communication path is established from a calling terminal over the four stage network, through a junctor circuit, and back over the four stage network to a called terminal. The junctors and associated C and D stage switching arrays (matrices) are arranged in ordered pairs related to the two sides of the junctors. Further, the ordered pairs are arranged in ordered pair groups to facilitate searching. The crosspoints of the switching arrays (matrices) comprise C-MOS driven J-FETs (FET packs) controlled and supervised by integrated circuit latch packs which provide distributed control and memory.

Abstract: A virtual encoding scheme for use in random access memories is disclosed. Data errors, incorrect memory word access errors, and errors resulting from multiple memory word access are all detectable through use of the encoding scheme. The novel approach includes the generation of two distinct check code fields which are stored along with the data. A first check code field is generated as a function of the data and is capable of reflecting all unidirectional data failures. A second check code field is generated as a function of the address of the memory word containing the data and is capable of reflecting incorrect memory word access. The two check fields can be stored either in the same physical memory location as the data or in a supplementary memory at an address numerically identical to that at which the data is kept. During readout, the two check fields are regenerated and compared to those previously stored.

Abstract: The data comprises 8-bit words, plus a leading bit as a start bit at a logic one, and a trailing bit for parity, for a total of 10 bits per group. A synchronizing circuit in the receiver selects a proper phase of clock signals for shifting the data bits into a shift register. An enable flip-flop for the synchronizing circuit is set in response to the start bit at the receiver input, and is reset when the start bit appears in the last bit position of the shift register.In a preferred embodiment, a clock signal is divided into three phases by a delay line. The synchronizing circuit has three flip-flops for selecting the phase when the enable flip-flop becomes set. These flip-flops enable gates for supplying the selected phase to the shift register. Delays are provided from the transmission line to the shift register and enable flip-flop inputs, so that the sampling is centered over each data bit.

Abstract: A telephone communication system reversibly converts input signals into adaptive delta modulated (hereafter ADM) signals and then into pulse code modulated signals. In one embodiment, an encoder of a telephone communication system receives analog signals, for example voice signals, in a comparator which also receives an analog signal from an integrator for periodically providing ADM signals. The ADM signals are provided to a pattern detector responsive to predetermined patterns of the ADM signals to supply a step size increase or decrease signal to the integrator which then generates the analog signal compared with the input signal for forming the ADM signals. Each signal from the pattern detector is a linear pulse code modulated (hereafter LPCM) signal representing a signal increment corresponding to that represented by the ADM signal. Each LPCM signal increment is then added to the total of each preceding LPCM signal increment to form LPCM signals representing the input analog signal.

Abstract: A telephone communication system reversibly converts input signals into adaptive delta modulated (hereafter ADM) signals and then into pulse code modulated signals. In one embodiment, a path for sending signals from a subscriber switch to a central office of a telephone communication system receives analog signals, for example voice signals, in a comparator which also receives an analog signal from an integrator for periodically providing ADM signals. The ADM signals are provided to means responsive to patterns of the ADM signals for providing a pattern controlled signal to the integrator which then generates the analog signal compared with input signal for forming the ADM signals. The ADM signals are also transmitted to digital means detecting the patterns of the ADM signals and responsive to each ADM signal and the detected patterns of the ADM signals for providing a linear pulse code modulated (hereafter LPCM) signal representing a signal increment corresponding to that represented by the ADM signal.