Abstract: A semiconductor device includes a T-gate disposed between drain and source regions and above a barrier layer to form a Schottky contact to the channel layer. A first inactive field mitigating plate is disposed above a portion of the T-gate and a second active field plate is disposed above the barrier layer and in a vicinity of the T-gate.

Abstract: A method and apparatus 10 for detecting the height of non-flat and transparent substrates using one or more reflectors 30 patterned on the surface of the substrate 40 and adjusting the position of the substrate in its holder based on measurement of the height of the reflectors in comparison to a calibration marker 60 on the holder and using appropriate spacers 50 with appropriate thickness to adjust the placement of the substrate at various locations to place the greatest portion of the substrate in an optimal focal range of the lithography system.

Abstract: An optical fiber amplifier includes a laser pump source for generating laser pump light; a fiber including an inner cladding layer optically coupled to a laser pump source for receiving laser pump light; a large mode area (LMA) core surrounded by the inner cladding, the LMA core including a confined region having a predetermined doping concentration of rare-earth ions for undergoing excitation to generate laser light when pumped by the laser pump light; and an outer cladding layer surrounding the inner cladding layer for substantially confining the laser pump light to the inner cladding and the LMA core. In a method of forming the optical fiber amplifier, a ratio of an area of the confined region to an area of the LMA core, and the predetermined doping concentration of the rare earth ions are selected so as to achieve a quantum efficiency (QE) gain factor of approximately 2, but such that the heat dissipation per unit length can be controlled by adjusting the area of the confined region.

Abstract: A pulsed coherent fiber array laser system that includes a beam generating sub-system that provides a signal pulse beam having pulses of the desired duration that is split into several fiber channels. Optical leakage between the pulses in each split beam is measured and locked to a reference beam by a phase sensing circuit and phase adjusters so that the phase of each fiber pulsed beam is aligned with the phase of the reference beam. A pulse clipper or filter is employed to remove the pulses in the fiber beams so that they do not saturate the phase sensing circuit. The beam generating sub-system can employ any suitable combination of devices to generate the signal beam and the reference beam, including continuous wave master oscillators, amplitude modulators, frequency shifters, injection seed oscillators, Q-switched lasers, reference oscillators, frequency lockers, wavelength division multiplexers, time gated switches, etc.

Abstract: The disclosure relates to a method for forming an intermediate lattice transition buffer layer. The method includes: (a) depositing a first graded InAlAs layer on a substrate at a first constant temperature, the first graded InAlAs layer having an In/AI composition ratio which increases across the buffer layer from a first level to a second level; (b) annealing at least the first graded InAlAs layer; (c) depositing the second graded InAlAs layer on the first graded InAlAs layer at the first constant temperature, the second graded InAlAs layer having an In/Al composition ratio which increases across the buffer layer from the second level to a third level; and (d) annealing at least the second graded InAlAs layer; the buffer layer being formed under Groups III/V overpressure.

Abstract: A semiconductor structure, such as a wafer-level package or a vertically stacked structure. The wafer-level package includes a substrate wafer on which an integrated circuit is formed. A cover wafer is bonded to the substrate wafer to provide a cavity between the substrate wafer and the cover wafer in which the integrated circuit is hermetically sealed. Vias are formed through the substrate wafer and make electrical contact with signal and ground traces formed on the substrate wafer within the cavity, where the traces are electrically coupled to the integrated circuit. Probe pads are formed on the substrate wafer outside of the cavity and are in electrical contact with the vias. A support post is provided directly beneath the probe pad so that when pressure is applied to the probe pad from the probe for testing purposes, the support post prevents the substrate wafer from flexing and being damaged.

Abstract: A wafer circuit, such as a wafer-level package, that includes a semiconductor substrate on which is fabricated one or more integrated circuits. A backside metal layer is deposited on the semiconductor substrate, and is electrically coupled to the integrated circuit by metallized vias extending through the substrate wafer. The backside metal layer is cut to provide electrically isolated backside metal layers for RF, DC and/or ground signals. An adhesion layer is deposited on the backside of the substrate before the metal layer is deposited so that the metal layer is firmly secured to the substrate, and resists peeling. The adhesion layer can be sputtered silicon, sputtered silicon nitride, silicon nitride deposited by chemical vapor deposition, nickel deposited by evaporation and nickel chromium deposited by evaporation.

Abstract: A method for fabricating wafer-level packages including lateral interconnects. The method includes precutting a cover wafer at the locations where the cover wafer will be completely cut through to separate the wafer-level packages. The cover wafer is bonded to the substrate wafer using bonding rings so as to seal the integrated circuit within a cavity between the cover wafer and the substrate wafer, where the precuts face the substrate wafer. The cover wafer is then cut at the precut locations to remove the unwanted portions of the cover wafer between the packages and expose contacts or probe pads for the lateral interconnects. The substrate wafer is then cut between the wafer-level packages to separate the packages.

Abstract: A wafer-level package that employs one or more integrated hydrogen getters within the wafer-level package on a substrate wafer or a cover wafer. The hydrogen getters are provided between and among the integrated circuits on the substrate wafer or the cover wafer, and are deposited during the integrated circuit fabrication process. In one non-limiting embodiment, the substrate wafer is a group III-V semiconductor material, and the hydrogen getter includes a titanium layer, a nickel layer, and a palladium layer.

Abstract: A method for mounting a dielectric substrate to a semiconductor substrate, such as mounting a dielectric antenna substrate to an MMIC semiconductor substrate. The method includes providing a thin dielectric antenna substrate having metallized layers on opposing sides. In one embodiment, carrier wafers are used to handle and maintain the dielectric substrate in a flat configuration as the metallized layers are patterned. The dielectric substrate is sealed to the semiconductor substrate using a low temperature bonding process. In an alternate embodiment, the metallized layers on the dielectric substrate are patterned simultaneously so as to prevent the substrate from curling.

Abstract: A device and method are disclosed for synthesizing a waveform having pulse segments. An exemplary generator can include units having a time delay element and pulse generator generating the pulse segments. An input divider divides an input signal into signal instances that propagate through the units and an output combiner combines pulse segments to form the waveform. The pulse generators include a sharpening circuit for sharpening a rising edge and a falling edge of the pulse segments. The sharpening circuit includes a tunable delay element coupled to a non-linear transmission line (NLTL). Another NLTL can be coupled in parallel with the tunable delay element and the first NLTL. The NLTLs include input sections coupled to anodes or cathodes of Schottky diode elements, and the respective cathodes or anodes are coupled to a signal ground.

Abstract: A method for performing signal processing for accelerating moving targets, in one implementation, encompasses a method for performing coherent integration of pulses within a CPI for SMTI radar. In an embodiment, the method comprises the steps of determining the Fast Fourier Transform (FFT) for each pulse, and multiplying the FFT by a pulse compression reference function.

Abstract: A semiconductor device (100) is formed on a semi-insulating semiconductor substrate (101) including a channel layer (104), a spacer layer (105), an electron supply layer (106), and a barrier layer (108). A composite layer (110) is formed over the barrier layer (108). A metal (116) is deposited over the composite layer (110). The metal (116) is annealed to promote a chemical reaction between the metal (116) and the composite layer (110) in which a portion of the metal sinks into the composite layer (110) and forms an ohmic contact with the composite layer.

Abstract: A frequency converter (100) is provided, comprising: a pulse generator (150) configured to receive a balanced local oscillator signal pair and to generate a balanced rectangular pulse signal pair having the reference frequency; and a mixer (160) configured to mix an input signal having an input frequency with the balanced rectangular pulse signal pair to generate an output signal having an output frequency. The input frequency is different from the output frequency, and the pulse generator and the mixer are formed on a single integrated circuit (120). The frequency converter may comprise a balanced local oscillator (110) configured to generate the balanced local oscillator signal pair. The balanced local oscillator may comprise: an unbalanced local oscillator (130) configured to provide an unbalanced local oscillator signal having the reference frequency; and a balun (140) configured to generate the balanced local oscillator signal pair based on the unbalanced local oscillator signal.

Abstract: Systems and methods for shifting the phase of incident light to induce a continuous phase variation in an azimuthal direction. A phase mask apparatus includes a conical mirror assembly and a flexible annular reflector that substantially surrounds at least a portion of the conical mirror assembly. The flexible annular reflector is configured to receive reflected light from the conical mirror assembly. A plurality of driver assemblies are operative to deform the flexible annular reflector as to produce the desired phase response in light reflected from the annular reflector.

Abstract: An optical architecture for a high-energy laser that directs a collimated laser beam through an aperture stop at a desired angle. In one embodiment, the optical architecture includes a single tilt mirror and three stationary mirrors that direct the laser beam in one dimension. The laser beam is reflected off of the mirrors in the same plane and is reflected off of the tilt mirror three times. The first two reflections off of the tilt mirror translate the beam and the third reflection causes the beam to be directed at the desired angle. In another embodiment, the optical architecture includes a single tip-tilt mirror and eight stationary mirrors that direct the beam in two dimensions. The laser beam is reflected off of the mirrors in two planes and is reflected off of the tip-tilt mirror three times. The first two reflections off of the tip-tilt mirror translate the beam and the third reflection causes the beam to be directed at the desired angle.

Abstract: A method to efficiently implement a reconfigurable electronic radio system (400) including resource assets (402-408, 410-416, 418, 420-426, 428) and a processor (428). The processor (428) generates RF control and switching control signals during each mission segment of an aircraft to create radio function threads through the resource assets (402-408, 410-416, 418, 420-426, 428) to realize the radio functions for that mission segment. The processor (428) may also be coupled to a master processor (440) that sends the processor (428) a radio function set selection signal. The radio function set selection signal identifies the radio function set that the processor (428) will implement through the resource assets (402-408, 410-416, 418, 420-426, 428). The processor (428) performs all signal, data, message, cryptographic and control processing required for the radio function threads being implemented by the resource assets.

Abstract: A semiconductor device that is fabricated by metamorphic epitaxial growth processes, and includes a combined graded base and active layer having a thickness less than 5000 ?. In one non-limiting embodiment, the semiconductor device is an HBT device that includes a combined doped graded buffer and sub-collector layer having a thickness less than 5000 ?, and a concentration of indium of about 86% at a top of the combined layer.

Abstract: A switching circuit (100) is provided, comprising: a signal coupler (110) configured to receive first and second input signals and provide first and second coupled signals; a first phase shifter (130) configured to shift a first phase of the first coupled signal by zero degrees or ninety degrees based on a first control signal to generate a first shifted signal; a second phase shifter (135) configured to shift a second phase of the second coupled signal by zero degrees or ninety degrees based on a second control signal to generate a second shifted signal; and a combiner (150) configured to combine the first and second shifted signals. The first coupled signal includes an in-phase copy of the first input signal and a ninety-degree-shifted copy of the second input signal; and the second coupled signal includes an in-phase copy of the second input signal and a ninety-degree-shifted copy of the first input signal.

Abstract: A method for assembling a bundle cable connector assembly that eliminates bird caging, wire threads extruding through a connector pin, loose wire threads, dielectric shield shrinking, etc. The method includes stripping the wire to create a birdcage preventative zone and an exposed tip with a crimping zone therebetween, and tinning the exposed wire at the birdcage preventative zone and the tip. The method then includes inserting the wire into a connector pin, and crimping the pin to the wire at the crimping zone using heat so that the tinning solder melts. The method then includes mounting the pin to a connector body and mounting a wire-locking device to the connector body to lock the pin to the connector body.