Abstract: One example includes a superconducting circuit. The circuit superconducting circuitry fabricated on a first surface of a circuit layer. The circuit layer includes a dielectric material. The circuit also includes a metal layer formed on a second surface of the circuit layer opposite the first surface and a through-substrate via (TSV) conductively coupled to the metal layer and extending through the circuit layer to the first surface. The circuit further includes a flux gasket conductively coupled to and extending from the TSV on the first surface proximal to the superconducting circuitry. The flux gasket can be configured to divert magnetic fields away from the superconducting circuitry.

Abstract: A Josephson junction (JJ) device is provided. The JJ device comprises an operating JJ, a first hydrogen-trapping JJ having a first end coupled to a first end of the operating JJ and a second end coupled to a first superconductor wire, and a second hydrogen-trapping JJ having a first end coupled to a second end of the operating JJ and a second end coupled to a second superconductor wire. The first hydrogen-trapping JJ and the second hydrogen-trapping JJ mitigates hydrogen diffusion into the operating JJ.

Abstract: One example includes a quantum lidar system. The system includes a beam generator configured to generate a signal beam and an idler beam and a beam combiner configured to generate a combined optical beam comprising the signal beam and the idler beam. The system also includes a lidar transmitter configured to transmit the combined optical beam to a target and a lidar receiver configured to receive the combined optical beam and a reflected beam of the combined optical beam reflected from the target to generate lidar data associated with the target.

Abstract: A method of forming a multi-chip system is disclosed. The method includes forming one or more bumps on respective conductive contact pads of a first electronic device, forming one or more mini-bumps on respective conductive contact pads of a second electronic device, and aligning respective one or more mini-bumps with respective one or more bumps. The method further includes performing a bump bonding process that exerts compression force on one or both the first electronic device and the second electronic device to compress the one or more mini-bumps into the one or more bumps to form one or more bump bond structures that bond the second electronic device to the first electronic device.

Abstract: Methods for fabricating high-temperature composite structures (e.g., structures comprising carbon-carbon composite materials or ceramic composite matrix (CMC) materials and configured for use at temperature at or exceeding about 2000° F. (1093° C.)) include forming precursor structures by additive manufacturing (“AM”) (e.g., “3D printing”). The precursor structures are exposed to high temperatures to pyrolyze a precursor matric material of the initial 3D printed structure. A liquid resin is used to impregnate the pyrolyzed structure, to densify the structure into a near-net final shape. Use of expensive and time-consuming molds and post-processing machining may be avoided. Large, unitary, integrally formed parts conducive for use in high-temperature environments may be formed using the methods of the disclosure.

Abstract: A radio frequency (RF) summer circuit having a characteristic impedance Z0 comprises first and second ports coupled by first and second resistances, respectively, to a junction. The circuit further comprises a series combination of a third resistance and a switch movable between open and closed positions and an amplifier having input and output terminals and operable in an off state and an on state wherein the series combination is coupled across the input and output terminals of the amplifier between the junction and a third port. The first resistance, second resistance, and the third resistance are all substantially equal to Z0/3. Further, when the switch is moved to the closed position and the amplifier is switched to the off state a passive mode of operation is implemented and when the switch is moved to the open position and the amplifier is switched to the on state an active mode of operation is implemented.

Abstract: Reciprocal quantum logic (RQL) bias-level sensors are fabricated on an RQL integrated circuit (IC) to sample AC or DC bias values provided to operational RQL circuitry on the RQL IC. The bias-level sensors, or samplers, include Josephson transmission lines (JTLs) or logic gates having strengthened or weakened bias taps as compared to bias taps of JTLs or logic gates in the operational RQL circuitry. Sampler JTLs or logic gates with weakened bias taps to AC clock resonators can have lower limits of their operational ranges placed near an optimal bias point at the centroid of the operating region of the operational RQL circuitry. Staging relative strengths of the bias taps of the samplers in an ensemble of samplers allows for outputs of wrapper circuitry to be indicative of whether a provided bias value is an improvement or optimization of the bias value when varied over a range.

Abstract: An output-amplifier-based reciprocal quantum logic (RQL) bias-level sensor is used to measure and/or calibrate bias parameters of AC and/or DC bias signals provided to RQL circuitry. The bias signals can include an output amplifier output bias current. The bias-level sensor includes a stack of DC SQUIDs that are supplied their inputs from outputs of respective Josephson transmission lines (JTLs) to which the SQUIDs are transformer-coupled. Staging relative strengths of the bias taps of the JTLs, or the critical currents of the Josephson junctions in the DC SQUIDs, allows an output voltage signal of the bias-level sensor to be indicative of whether a provided bias value is an improvement or optimization of the bias value when varied over a range. The outputs of two such bias-level sensors driven by I and Q clocks can be compared to adjust AC bias amplitudes of the clocks. Relative clock phase can be similarly adjusted.

Abstract: Shift register elements of a phase-mode bit-addressable sensing register sample varied AC or DC bias values provided to operational RQL circuitry on the RQL IC via clock resonators or DC bias lines. The shift register can be constructed of phase-mode D flip-flops and JTLs as data and clock lines. A method of using the sensing register includes shifting in a data bit pattern while a bias parameter (e.g., AC amplitude, DC value, or phase) is set to a nominal value; stopping the logical clock that controls the shifting of values through the sensing register, varying the bias parameter value, inputting one assertion SFQ pulse or reciprocal pulse pair into the logical clock, restoring the bias parameter to the nominal value, restarting the logical clock to shift out an output data bit pattern, and observing the output data bit pattern to determine the effect of the bias parameter value change.

Abstract: Pulse-generator-based reciprocal quantum logic (RQL) bias-level sensors are fabricated on an RQL integrated circuit (IC) to sample AC or DC bias values provided to operational RQL circuitry on the RQL IC. The bias-level sensors include pulse generators having strengthened or weakened bias taps (transformer couplings to RQL AC clock resonators or DC bias lines) as compared to bias taps of Josephson transmission lines in the operational RQL circuitry, or Josephson junctions (JJs) with larger or smaller critical currents as compared to JJs in the operational RQL circuitry. Pulse generators with weakened bias taps or larger JJs can have lower limits of their operational ranges placed near an optimal bias point at the centroid of the operating region of the operational RQL circuitry. The bias-level sensors can be staged by relative strength to indicate whether a provided bias value is an improvement when varied over a range.

Abstract: A thermal energy storage system including an enclosure having an internal volume. An incompressible phase change material (PCM) is provided within the internal volume of the enclosure, where the PCM contracts into a solid state when its temperature falls below a certain temperature and expands into a liquid state when its temperature goes above the certain temperature. An elastic bladder is positioned adjacent to the PCM within the internal volume of the enclosure and is filled with a compressible material, where the PCM pushes against the bladder when it is expanded to the liquid state and causes the compressible material to be compressed within the bladder and the enclosure.

Abstract: A method for generating light emission is provided. The method includes providing a transistor element including collector, emitter, and base regions, a quantum cascade region between the base and collector regions, and quantum well structures for interband emission within the base or emitter regions. A waveband controller applies, via first and second electrodes with respect to the collector and base regions, a first electrical signal to control a base-collector junction bias level and select between first and second base-collector bias levels. Selection of the first base-collector bias level causes at least one of the emitter and base regions to produce interband-based light emission having a first wavelength of a first wavelength band. Selection of the second base-collector bias level causes the quantum cascade region to produce intraband-based light emission having a second wavelength of a second wavelength band.

Abstract: Shift register elements of a phase-mode bit-addressable sensing register sample varied AC or DC bias values provided to operational RQL circuitry on the RQL IC via clock resonators or DC bias lines. The shift register can be constructed of phase-mode D flip-flops and JTLs as data and clock lines. A method of using the sensing register includes shifting in a data bit pattern while a bias parameter (e.g., AC amplitude, DC value, or phase) is set to a nominal value; stopping the logical clock that controls the shifting of values through the sensing register, varying the bias parameter value, inputting one assertion SFQ pulse or reciprocal pulse pair into the logical clock, restoring the bias parameter to the nominal value, restarting the logical clock to shift out an output data bit pattern, and observing the output data bit pattern to determine the effect of the bias parameter value change.

Abstract: In the described examples, a compiled image scaler includes a set of machine executable instructions that generate a scaled image that is a scaled version of a source image with integer and bitwise operations. The compiled image scaler employs filtering to blend colors of adjacent pixels in the source image to generate the scaled image, and each filtering operation concurrently scales three color channels of a pixel in the source image.

Abstract: A multilayered metal nanowire array including a plurality of stacked and separated nanowire array layers each including a plurality of vertically aligned metal nanowires, and a lateral interposer positioned in a gap between each pair of adjacent nanowire array layers and being thermally coupled to the nanowires in the adjacent layers so that the lateral interposers provide thermal conduction between the nanowire array layers and laterally across each nanowire array layer. The nanowire array layers between the interposers can have the same or different thicknesses, the diameter and density of the nanowires can be the same or different, and the nanowire metal can be the same or different.

Abstract: One example includes an atomic optical reference system. The system includes an optical system comprising a laser configured to generate an optical beam. The system also includes a vapor cell comprising alkali metal atoms that are stimulated in response to a modulated beam corresponding to an amplitude-modulated version of the optical beam. The system also includes a detection system configured to monitor at least one detection signal corresponding to light emitted from or absorbed by the vapor cell and to generate at least one feedback signal in response to the at least one detection signal. The system further includes a beam modulator configured to amplitude-modulate the optical beam to generate the modulated beam and to frequency shift the optical beam to generate an output beam having a stable frequency in response to the at least one feedback signal.

Abstract: This disclosure relates to systems and methods for current source temperature compensation for use during cryogenic electronic testing. A temperature compensation circuit can provide a temperature compensation signal to a current source circuit configured to provide an electrical current for testing a cryogenic device under test to compensate for temperature effects on the current source circuit based on a time constant adjustment signal. The time constant adjustment signal can adjust a time constant of the temperature compensation circuit to delay by a given amount of time that the temperature compensation circuit compensates for the temperature effects on the current source circuit. A controller can be configured to execute a temperature compensation method to provide the time constant adjustment signal based on at least one temperature signal characterizing a temperature of an environment that includes the current source circuit or a temperature of the current source circuit.

Abstract: One example includes a radar image interface system. The system includes an image processor configured to receive synthetic aperture radar (SAR) image data associated with a region of interest and to generate a radar image of the region of interest based on the SAR image data. The image processor can be further configured to divide the radar image into a plurality of sequential units corresponding to respective zones of the region of interest. The system also includes a display system configured to display zoomed sequential units corresponding to respective zoomed versions of the sequential units of the radar image to a user. The system further includes an input interface configured to facilitate sequentially indexing through each of the zoomed versions of the sequential units on the display system in response to an indexing input provided by the user.

Abstract: One example includes a radar image interface system. The system includes an image processor configured to receive synthetic aperture radar (SAR) image data associated with a region of interest and to generate a radar image of the region of interest based on the SAR image data. The image processor can be further configured to divide the radar image into a plurality of sequential units corresponding to respective zones of the region of interest. The system also includes a display system configured to display zoomed sequential units corresponding to respective zoomed versions of the sequential units of the radar image to a user. The system further includes an input interface configured to facilitate sequentially indexing through each of the zoomed versions of the sequential units on the display system in response to an indexing input provided by the user.

Abstract: A method of forming a superconducting structure is provided that includes forming a superconducting element in a first dielectric layer, forming a protective pad formed from a resistive material over at least a portion of the superconducting element, forming a second dielectric layer overlying the first dielectric layer, and etching an opening through the second dielectric layer to the protective pad, such that no portion of the superconducting element is exposed in the opening. A cleaning process is performed on the superconducting structure, and a contact material fill with a resistive material is performed to fill the opening and form a resistive element in contact with the superconducting element through the protective pad.