Abstract: An reciprocal quantum logic (RQL) gate circuit has a first stage having four logical inputs asserted based on receiving positive single flux quantum (SFQ) pulses and storing the SFQ pulses in respective storage loops each associated with a logical input, and a second stage having two more storage loops. First and second logical decision Josephson junctions (JJs) make determinations based on signals stored in the first-stage storage loops. A third logical decision JJ makes a third determination based on the first and second determinations. Each logical decision JJ triggers based on biasing provided by one or more currents stored in its associated storage loops and a bias signal having an AC component. The second stage asserts an output based on the triggering of the third logical decision JJ. Four-input AND, OR, AO22, and OA22 gates are thereby provided.

Abstract: An exemplary FET includes a substrate and multiple vertically stacked layer groups with each layer group having a quantum well semiconductive layer and a nonconductive layer adjacent the first quantum well semiconductive layer. Conductive source and drain electrodes in conductive contact with the semiconductive layers. A 3-dimensional ridge of the stacked layer groups is defined between spaced apart first and second trenches which are between the source and drain electrodes. A continuous conductive side gate is disposed on the sides and top of the ridge for inducing a field into the semiconductive layers. A gate electrode is disposed in conductive contact with the conductive side gate.