Abstract: A sub-surface membrane deposition device including a movable frame, at least one chisel attached to the frame, hydraulics to raise and lower the at least one chisel from the frame, and a membrane deployable to a sub-surface level by the at least one chisel as the movable frame is moved. Also provided is a method of deposing a membrane to a sub-surface level that includes providing a movable frame, at least one chisel attached to the frame, hydraulics to raise and lower the at least one chisel from the frame, and a membrane. The method including lowering the at least one chisel with the hydraulics to the sub-surface level, moving the frame and at least one chisel forward, and deploying the membrane to the sub-surface level with the at least one chisel.

Abstract: A system for reducing the effects of a blast wave includes armor plating configured to face a supersonic blast wave. The armor plating has a surface consisting of alternating tall and short peaks with valleys between the peaks. The peaks and valleys are positioned such that the supersonic blast wave reflects from the side surfaces of the tall peaks as a regular reflection that at least partially suppresses Mach reflection of the supersonic wave caused by the short peaks and the valleys. The surface may also be designed to not trap reflected waves. The valleys can be parabolic shaped to deflect and/or dissipate transonic flow that follows the blast wave front.

Abstract: A system for reducing the effects of a blast wave includes armor plating configured to face a supersonic blast wave. The armor plating has a surface consisting of alternating tall and short peaks with valleys between the peaks. The peaks and valleys are positioned such that the supersonic blast wave reflects from the side surfaces of the tall peaks as a regular reflection that at least partially suppresses Mach reflection of the supersonic wave caused by the short peaks and the valleys. The surface may also be designed to not trap reflected waves. The valleys can be parabolic shaped to deflect and/or dissipate transonic flow that follows the blast wave front.

Abstract: A unit cell for a Read-In Integrated Circuit employs a signal sampling circuit with a voltage input controlled by a first switch, a capacitor charged by the voltage input and a linear amplifier connected to the capacitor. An output through a second switch samples the capacitor as the input signal for a transistor cascade for emitter current supply incorporating a first transistor receiving the input signal and a second transistor serially connected to the first transistor with a parallel resistor. The second transistor is maintained in saturation for a first portion of the input signal range with the first transistor acting as a source follower for that range. Linear current flow through the resistor results allowing high resolution control in the low current range.

Abstract: A composite armor plate includes a fracture layer placed adjacent to a ceramic layer. The ceramic layer provides a ballistic resistant layer that receives a ballistic impact and propagates a compression wave. The fracture layer is placed behind the ceramic layer and absorbs a portion of the compression wave propagating out in front of the ballistic impact. The absorbed compression wave causes the fracture layer to at least partially disintegrate into fine particles, which dissipates energy in the process. To cause a higher degree of fracturing (and thus larger dissipation of compression wave energy) the fracture layer includes a plurality of resonators embedded in a fracture material.

Abstract: An infrared camera system for low contrast employs a focal plane array (FPA) of a plurality of detector diodes. A read out integrated circuit (ROIC) including a plurality of integration switches is connected to the plurality of detector diodes. A frame mean calculator receives raw data from the FPA and an integration time servo receives a frame mean from the frame mean calculator and a preprogrammed target mean. The integration time servo compares the frame mean and target mean and provides an integration time output to the ROIC responsive to the comparison for control of the integration switches.

Abstract: An armor plate transforms projectile energy into solid-state lattice waves and facilitates absorption of these waves at different wavelengths. For high frequency lattice waves, dopants are used for absorbing the lattice waves and converting them to thermal energy. Heavy dopants and layered materials can also be use for reflecting lattice waves to facilitate attenuation through absorption. A spreading layer can also be used for dispersing non-absorbed lattice waves.

Abstract: A method for super resolution enhancement of infrared imaging data employing an image array having simultaneous, high speed, randomly addressable windows of pixels for small regions of interest (ROI) within a large imaging sensor field of view. Data is retrieved from the ROI window pixels at an increased data rate and the array is dithered to produce sub-pixel motion consistent with the increased data rate. A selected super resolution (SR) algorithm is then applied to the data retrieved from the ROT window pixels at the increased data rate. The reduced data set substantially relieves the computational load on the processor compared with the requirement of performing SR processing on the entire frame of image data. The output from the SR algorithm is either used to replace the LR frame data in the image or is displayed as a separate image to the user.

Abstract: A dual speed Read-Out Integrated Circuit employs a native pixel array with associated high resolution integration circuits for each pixel and a superpixel array created within the native pixel array by combination of native pixels for charge sharing integration in reduced resolution integration circuits simultaneously with the integration of the high resolution integration circuits. Switching control for readout of the high resolution integration circuits is accomplished at a first frame rate and switching control for readout of the reduced resolution integration circuits is accomplished at a second higher frame rate.

Abstract: A dual mode amplifier for photodiode output reads a photodiode providing a current input. An integration capacitor is connected to receive the current input and connected to a voltage output node. An input capacitor is also connected to receive the voltage input and drives an operational amplifier having an output connect to the voltage output node. A correlated double-sample (CDS) capacitor is connected to the voltage output node and a sample and hold circuit incorporating a sample and hold capacitor for sampling the CDS capacitor. A log function on (LOGON) switch is connected between the operational amplifier output and the voltage output node and a reset switch connected to short the photodiode.

Abstract: An armor plate includes at least four layers configured to generate a compression wave that is dissipated in a fracture player. The armor plate includes a deformable layer of a material having an elongation before failure of 20% or more; a transparent ceramic layer adjacent the deformable layer; a transparent fracture layer adjacent the ceramic layer; and a transparent spall liner backing the fracture layer.

Abstract: A Read-In Integrated Circuit scene generator incorporates an array of unit cells, with each cell having a switching control circuit. An array of emitting elements is associated with the unit cells and each element is connected with a lead to the switching control circuit of the associated cell. A first electrically conducting overlayer is deposited substantially covering the array of unit cells and connected for current supply. Each emitting element is connected to the first conducting overlayer and the first conducting overlayer includes vias through which each connecting lead from the emitting element to the switching control circuit extends. A second electrically conducting overlayer is deposited substantially covering the array of unit cells and connected for current return. Each switching control circuit is connected to the second conducting overlayer. The second conducting overlayer also has vias through which each lead from the emitting element extends to the switching circuit.

Abstract: A unit cell for a Read-In Integrated Circuit employs a signal sampling circuit with a voltage input controlled by a first switch, a capacitor charged by the voltage input and a linear amplifier connected to the capacitor. An output through a second switch samples the capacitor as the input signal for a transistor cascade for emitter current supply incorporating a first transistor receiving the input signal and a second transistor serially connected to the first transistor with a parallel resistor. The second transistor is maintained in saturation for a first portion of the input signal range with the first transistor acting as a source follower for that range. Linear current flow through the resistor results allowing high resolution control in the low current range.

Abstract: A variable acuity imager incorporates an array of detection elements for light energy, in the visible, infrared, ultraviolet, or light energy in another region of the electromagnetic spectrum with a means to change the spatial configuration of the array to include “superpixels” by combining energy detected by adjacent elements, thus permitting any number of high-resolution “foveal” regions to be placed within the confines of the focal plane array and moved around at the frame rate of the imaging device. Detectors to measure the pitch, yaw and roll angle rates of background imagery using velocity-sensing circuitry are employed for variation of the foveal regions to accommodate motion of the array.

Abstract: A longwave infrared (LWIR) camera system incorporates a prism having a reflecting face with an internal surface and an external surface, an input face and an output face. A visible light source provides light to the prism input face and an image detector is positioned to receive light from the prism output face. A plurality of bi-metal cantilevers are arranged in a MEMS array immediately adjacent the external surface of the reflecting face of the prism. Each of the bi-metal cantilever deflects based on absorbed infrared energy to contact the outer surface of the reflecting face. A CMOS image sensor is employed as the image detector.

Abstract: A variable acuity imager incorporates an array of detection elements for light energy, in the visible, infrared, ultraviolet, or light energy in another region of the electromagnetic spectrum with a means to change the spatial configuration of the array to include “superpixels” by combining energy detected by adjacent elements, thus permitting any number of high-resolution “foveal” regions to be placed within the confines of the focal plane array and moved around at the frame rate of the imaging device. Detectors to measure the pitch, yaw and roll angle rates of background imagery using velocity-sensing circuitry are employed for variation of the foveal regions to accommodate motion of the array.

Abstract: A variable acuity imager incorporates an array of detection elements for light energy, in the visible, infrared, ultraviolet, or light energy in another region of the electromagnetic spectrum with a means to change the spatial configuration of the array to include “superpixels” by combining energy detected by adjacent elements, thus permitting any number of high-resolution “foveal” regions to be placed within the confines of the focal plane array and moved around at the frame rate of the imaging device. Detectors to measure the pitch, yaw and roll angle rates of background imagery using velocity-sensing circuitry are employed for variation of the foveal regions to accommodate motion of the array.

Abstract: In accordance with one or more embodiments of the present invention, a technique fabricating a magnetoresistive memory device, where the magnetoresistive memory device has a magnetic memory element and a plurality of conductors for at least one of reading and writing the magnetic memory element. The plurality of conductors include a first conductor at least partially located at a first side of the magnetic memory element for reading the magnetic memory element, a second conductor at least partially located at a second side of the magnetic memory element for reading the magnetic memory element, a third conductor at least partially located at the second side of the magnetic memory element for writing the magnetic memory element, and a fourth conductor at least partially located at the first side of the magnetic memory element for writing the magnetic memory element. The first conductor is formed before the fourth conductor.

Abstract: A variable acuity imager incorporates an array of detection elements for light energy, in the visible, infrared, ultraviolet, or light energy in another region of the electromagnetic spectrum with a means to change the spatial configuration of the array to include “superpixels” by combining energy detected by adjacent elements, thus permitting any number of high-resolution “foveal” regions to be placed within the confines of the focal plane array and moved around at the frame rate of the imaging device. Detectors to measure the pitch, yaw and roll angle rates of background imagery using velocity-sensing circuitry are employed for variation of the foveal regions to accommodate motion of the array.

Abstract: In accordance with one or more embodiments of the present invention, a technique fabricating a magnetoresistive memory device, where the magnetoresistive memory device has a magnetic memory element and a plurality of conductors for at least one of reading and writing the magnetic memory element. The plurality of conductors include a first conductor at least partially located at a first side of the magnetic memory element for reading the magnetic memory element, a second conductor at least partially located at a second side of the magnetic memory element for reading the magnetic memory element, a third conductor at least partially located at the second side of the magnetic memory element for writing the magnetic memory element, and a fourth conductor at least partially located at the first side of the magnetic memory element for writing the magnetic memory element. The first conductor is formed before the fourth conductor.