Abstract: A motion estimation circuit and a motion estimation processing element are provided. The latch module in the motion estimation circuit has n pieces of m-stage shift registers. Each shift register receives a current block data and transmits the received current block data to next stage according to a timing. The processing module has a plurality of processing elements (PEs), which are divided into (m+1) groups. The PEs of the i-th group receive the left search window data and the right search window data and are coupled to the input ends and the output ends of the i-th stage of latches, wherein 0<i?m. Each PE compares the similarity degree between the corresponding candidate block in the search window and the current block and outputs the processed result, respectively. The comparing unit receives and compares the processed results for outputting a first comparison result.

Abstract: A voltage interpolation buffer for interpolating voltages by adjusting ratio of bias currents includes a first difference voltage to current unit for outputting corresponding difference current according to a first voltage, a first bias current and voltage of a voltage output end, a second difference voltage to current unit for outputting corresponding difference current according to a second voltage, a second bias current and the voltage of the voltage output end, and a current to voltage unit coupled to the first difference voltage to current unit, the second difference voltage to current unit and the voltage output end for outputting a interpolation result of the first voltage and the second voltage corresponding to a ratio of the first bias current and the second bias current according to the difference currents outputted by the first difference voltage to current unit and the second difference voltage to current unit.

Abstract: The invention relates to a data processing system which comprises a memory module and a microprocessor. The memory modules comprise at least one low-speed memory and one high-speed memory; both store an interrupt vector table individually for recording the entry instruction of interrupt service routines. The microprocessor comprises a central processing unit (CPU) and a memory controller with a re-addressing device. Once an interruption occurs, the CPU generates and sends an interrupt vector address to the memory controller. If the vector is located in the range of interrupt vector table, the re-addressing device sends an enable signal to the high-speed memory to enable the CPU to fetch the entry instruction of interrupt service routines from the high-speed memory, not from the pre-determined low-speed memory. Hence, the interrupt latency is reduced.