Abstract: The present disclosure relates to a method for driving a display panel. The method includes: determining whether or not to perform a refresh operation on a current frame to be displayed by the display panel; and when it is determined not to perform the refresh operation on the current frame, refraining from sending a frame scanning start signal (e.g., an STV signal) to the display panel, and reducing the frequency of a gate clock signal or fixing the gate clock signal to a specific voltage level.

Abstract: An oscillating signal adjusting circuit is provided. The oscillating signal adjusting circuit is adapted to generate an internal clock signal of a touch and display driver integrated circuit and includes a frequency shift circuit and a spread spectrum control circuit. The frequency shift circuit acquires a first setting data indicated by a mode control signal, and determines whether to shift a frequency of the input clock signal according to the first setting data to generate a first output clock signal. The spread spectrum control circuit to acquires a second setting data indicated by the mode control signal, and determines whether to perform a spreading spectrum operation on the first output clock signal according to the second setting data to generate the internal clock signal. The mode control signal has a first voltage level in a display period and has a second voltage level in a touch sensing period.

Abstract: A power supply device and an operation method thereof are provided. The power supply device includes a charge pump circuit and a power supply circuit. The power supply circuit supplies a first power voltage to the charge pump circuit. The charge pump circuit converts the first power voltage into a second power voltage so as to supply the second power voltage to an application circuit. The power supply circuit detects the second power voltage or an output current output by the charge pump circuit to obtain a detection result. The power supply circuit dynamically adjusts the first power voltage based on the detection result.

Abstract: A signal converter includes a first capacitor, a second capacitor, a first switch to a fourth switch, and a first feedback control circuit to a fourth feedback control circuit. The first switch and the second switch are coupled between a reference voltage end and an output end in series. The first switch and the second switch are respectively controlled by a first feedback control signal and a second feedback control signal. The third switch and a fourth switch are respectively controlled by a third feedback control signal and a fourth feedback control signal. The first feedback control circuit provides the first feedback control signal. The second feedback control circuit provides the second feedback control signal. The third feedback control circuit provides the third feedback control signal. The fourth feedback control circuit provides the fourth feedback control signal.

Abstract: A method of compensating a display panel includes providing a refresh control signal to configure a first area and a second area of the display panel; and providing an initial signal to the display panel. The initial signal includes a first initial voltage to initialize the first area before a first data operation, and a second initial voltage to initialize the second area before a second data operation.

Abstract: An image alignment method is proposed. The method includes to obtain a first image and a second image of a scene, identify a first overlapping region in the first image and a second overlapping region in the second image, distribute anchor points over the first overlapping region and the second overlapping region at regular intervals, and align the first image and the second image according to the anchor points in the first overlapping region and the second overlapping region, where the first overlapping region and the second overlapping region are an overlapping region between the first image and the second image.

Abstract: An image calibration system including an image capturing device, a calibration unit, a mount plate, and a processor are provided. The image capturing device includes at least one camera module. The processor is configured to: control the at least one camera module to capture an image of the calibration unit; determine whether there is any other part of the calibration unit not captured yet based on images already captured by the at least one camera module; and in response to determining that there is at least a part of the calibration unit not shown in the captured images, control the at least one camera module to capture another image of the calibration unit. The processor further calculates image calibration parameters based on a sufficient number of qualified images captured by the at least one camera module. The image calibration parameters are used for calibrating image distortion.

Abstract: A universal serial bus (USB) device, coupled to a USB host, includes a transceiver, receiving a data signal having a first frequency from the USB host, wherein the data signal comprises a plurality of specific packets with a periodic characteristic; a packet detector, coupled to the transceiver, receiving the data signal through the transceiver, configured to generate a reference signal according to the periodic characteristic of the plurality of specific packets; and a frequency-locked loop (FLL) circuit, coupled to the transceiver and the packet detector, configured to generate a clock signal having a second frequency according to the reference signal; wherein the first frequency is substantially equal to the second frequency. In other words, the second frequency is adjusted to approach the first frequency, and a frequency difference between the first frequency and the second frequency is smaller than 500 ppm.

Abstract: A computer device, an edge device, and a method for an artificial intelligence (AI) inference on a video stream are proposed. The computing device at least includes a first processor and a second processor. The first processor is configured to continuously receive a main video stream. The second processor is configured to perform scaling on the main video stream to generate a scaled video stream and to perform AI inference on a first frame of the scaled video stream to generate an AI inference result for a second frame of the main video stream, where the second frame of the main video stream is a frame corresponding to a time point when or after the AI inference result is generated.

Abstract: A machine learning method using pooling on channel attention includes inputting a first residual input to convolution layers of a first residual network to generate a first convolved output, and inputting the first convolved output to a first pooling layer to generate a first pooling vector. This results in a decrease in both computational time and memory usage, which in turn boosts the efficiency and performance of the machine learning model.

Abstract: A control circuit for a feed-forward equalizer (FFE) includes an FFE controller and an impedance control loop. The FFE has a plurality of tap drivers commonly coupled to an output terminal. The FFE controller, which receives a basic current from a current generator, includes a current digital-to-analog converter (DAC) and a current mirror. The current DAC generates a reference current according to the basic current. The current mirror mirrors the reference current to generate at least one first reference voltage, and outputs the at least one first reference voltage to at least one first tap driver among the plurality of tap drivers. The impedance control loop, coupled to the FFE controller, generates a second reference voltage according to the at least one first reference voltage, and outputs the second reference voltage to at least one second tap driver among the plurality of tap drivers.

Abstract: A sense amplifier circuit including a sense amplifier and a control circuit is provided. The sense amplifier is configured to detect input data. The control circuit is coupled to the sense amplifier. The control circuit outputs a control signal to control the sense amplifier to detect the input data. The control circuit controls whether the sense amplifier performs a pre-charge operation or a pre-discharge operation based on the input data of a previous cycle and a current cycle.

Abstract: A driving device is provided. The driving device includes a driver and a timing controller (TCON). The driver is coupled to a pixel circuit and a backlight circuit of a display panel. The TCON is coupled to the driver. In a frame cycle, after a delayed interval, the TCON outputs output image data to the driver, such that the driver drives the pixel circuit and the backlight circuit according to the output image data and backlight image data at the same time. Alternatively, when the driver drives the pixel circuit, after an interval based on dummy data of the backlight image data, the driver drives the backlight circuit according to available data of the backlight image data.

Abstract: A display device, a display driving integrated circuit (IC), and an operating method of a display driving IC are provided. The display driving IC receives a data stream and an external horizontal synchronization signal from a processor, where the data stream includes display frame data, vertical synchronization information, and horizontal synchronization information. The display driving IC generates an internal vertical synchronization signal based on the vertical synchronization information and the horizontal synchronization information. The display driving IC dynamically updates a delay value based on a phase relationship among the vertical synchronization information, the horizontal synchronization information, and the external horizontal synchronization signal. The display driving IC delays the external horizontal synchronization signal based on the delay value to generate an internal horizontal synchronization signal.

Abstract: A display driver integrated circuit (DDIC) receives a data stream, where the data stream includes display frame data, vertical synchronization information, and horizontal synchronization information. The DDIC generates an internal horizontal synchronization signal based on the horizontal synchronization information. The DDIC starts counting a first counting time length and a second counting time length from a same horizontal synchronization pulse of the internal horizontal synchronization signal, where the first counting time length is less than a horizontal time length defined by the internal horizontal synchronization signal, and the second counting time length is greater than the horizontal time length. At the end of the first counting time length, the DDIC pulls a gate clock signal from a first level to a second level. At the end of the second counting time length, the DDIC pulls the gate clock signal back from the second level to the first level.

Abstract: A timing control circuit includes a receiving circuit and a line memory. The line memory is configured for receiving a signal, outputting a first data signal corresponding to a first frame of the signal to drive at least one data line, and outputting a second data signal corresponding to a second frame of the signal. After a first frame rate of the first frame is determined to be higher than a second frame rate of the second frame, a switch from a long V mode to a long H mode takes place, such that the first data signal corresponds to the long V mode and the second data signal corresponds to the long H mode. After the first frame rate is determined to be lower than the second frame rate, a switch from the long H mode to the long V mode takes place.

Abstract: A driving method for a display panel, display driving device, and display device are provided. The method includes: in a first clock cycle, displaying to-be-displayed data for (N?M)-th pixel row and obtaining to-be-displayed data for N-th pixel row expected to be displayed after a preset delay period from a start time of the first clock cycle, the preset delay period lasting for M clock cycles; and providing gate driving signals for (N?M+1)-th to (N1?1)-th pixel rows and inhibiting providing gate driving signals for N1-th to N2-th pixel rows in response to an error event in the to-be-displayed data for N-th pixel row, wherein a gate driving signal for each pixel row includes a pre-charging period and a displaying period, the pre-charging period lasts for Q clock cycles, and wherein N?M+Q+1?N1?N, and N?N2?T (a number of the plurality of pixel rows).

Abstract: A touch display device is provided. The touch display device includes a touch display panel and a driver circuit. The touch display panel includes a control transistor coupled to a common electrode through a liquid crystal capacitor. The driver circuit is coupled to the touch display panel, and outputs a first driving signal to a first terminal of the control transistor. When the touch display panel switches from a first operational cycle to a first transition interval, the driver circuit adjusts the first driving signal to change a voltage of the first terminal of the transistor from a first voltage to a second voltage different from the first voltage to adjust a voltage of the common electrode.

Abstract: An operating method of a display driver circuit is provided. The display driver is configured to drive a display panel. The display panel has at least a first area and a second area. The operating method includes: in a first mode, refreshing the first area and the second area in a first frame rate; and in a second mode, refreshing the second area in a second frame rate and refreshing the first area in a third frame rate. The second frame rate is higher than the first frame rate and the third frame rate. In addition, a clock signal to drive a plurality of scan lines stops toggling pules corresponding to the first area.

Abstract: A driving integrated circuit includes a first output buffer and a second output buffer. The first output buffer generates a first start pulse signal to a first scan driving circuit, so that the first scan driving circuit generates a first plurality of scan driving signals to a plurality of first scan lines of a display panel. The second output buffer generates a second start pulse signal to a second scan driving circuit, so that the second scan driving circuit generates a second plurality of scan driving signals to a plurality of second scan lines of the display panel. The earliest second scan line of the second scan lines is driven after the first scan lines are driven. A plurality of driving units of the second output buffer are respectively controlled to generate the second start pulse signal having a driving ability less than a driving ability of the first start pulse signal.