Patents Assigned to Novelies, LLC
  • Memory row and column redundancy
    Patent number: 7738308
    Abstract: In one embodiment, a memory includes a row and/or column redundancy architecture that uses binary cells to indicate whether a given row or column of memory cells is faulty. The binary cell is adapted to store a “repair true” signal in response to a conventional access to the corresponding row or column and also the assertion of a set signal.
    Type: Grant
    Filed: January 18, 2008
    Date of Patent: June 15, 2010
    Assignee: Novelies, LLC
    Inventors: Morteza Cyrus Afghahi, Esin Terzioglu, Gil I. Winograd