Abstract: This invention provides a high throughput PECVD process for depositing TEOS films in a multi-station sequential deposition chamber. The methods significantly reduce the number of particles in the TEOS films, thereby eliminating or minimizing small bin defects. The methods of the invention involve dedicating a first station for temperature soak while flowing purge gas. Stopping the flow of reactant gas and flowing the purge gas for station 1 eliminates TEOS condensation on a cold wafer surface and significantly reduces the number of defects in the film, particularly for short temperature soaks.

Abstract: Capping protective self aligned buffer (PSAB) layers are layers of material that are selectively formed at the surface of metal layers in a partially fabricated semiconductor device. Encapsulating PSAB layers are formed not only at the surface of the metal layers, but also within the unexposed portions of the metal lines. Encapsulating PSAB layer, for example, can surround the metal line with the PSAB material, thereby protecting interfaces between the metal line and diffusion barriers. Encapsulating PSAB layers can be formed by treating the exposed surfaces of metal lines with GeH4. Capping PSAB layers can be formed by treating the exposed surfaces of metal lines with SiH4. Interconnects having both a silicon-containing capping PSAB layer and a germanium-containing encapsulating PSAB layer provide good performance in terms of adhesion, resistance shift, and electromigration characteristics.

Abstract: A method is provided for manufacturing removable contact structures on the surface of a substrate to conduct electricity from a contact member to the surface during electroprocessing. The method comprises forming a conductive layer on the surface. A predetermined region of the conductive layer is selectively coated by a contact layer so that the contact member touches the contact layer as the electroprocessing is performed on the conductive layer.

Abstract: A method for forming a silicon-based dielectric film on a substrate with a single deposition process operation using pulsed plasma enhanced chemical vapor deposition (PECVD) wherein the high frequency radio frequency power of the plasma is pulsed, allows enhanced control, efficiency and product quality of the PECVD process. Pulsing the high frequency RF power of the plasma reduces the deposited film thickness per unit time the high frequency RF power of the plasma is on. This yields silicon-based dielectric films that are both thin and conformal.

Abstract: A method of depositing material on a substrate comprises providing a reactor with a reaction chamber having a first volume, and contacting a surface of a substrate in the reaction chamber with a first precursor at the first chamber volume to react with and deposit a first layer on the substrate. The method further includes enlarging the reaction chamber to a second, larger volume and removing undeposited first precursor and any excess reaction product to end reaction of the first precursor with the substrate.

Abstract: Methods of preparing a carbon doped oxide (CDO) layer with a low dielectric constant (<3.2) and low residual stress without sacrificing important integration properties such as refractive index and etch rate are provided. The methods involve, for instance, providing a substrate to a deposition chamber and exposing it to TMSA, followed by igniting and maintaining a plasma in a deposition chamber using radio frequency power having high and low frequency components or one frequency component only, and depositing the carbon doped oxide film under conditions in which the resulting dielectric layer has a net tensile stress of less than about 40 MPa, a hardness of at least about 1 GPa, and a SiC:SiOx bond ratio of not greater than about 0.75.

Abstract: Liquid detection sensors are attached to both sides of a robotic arm end effector of a semiconductor wafer process system. The sensor mechanism or probe is situated on the front side and backside of the end effector, designed with electrical lines that are traced onto a polyester base material. The electrical lines are positioned in a serpentine formation. The high conductance of the sulfuric acid in the copper sulfate solution acts as the conductor between the traced lines. When the conductive liquid comes in contact with the traced lines, the lines short and the sensor activates or turns on.

Abstract: A conductive planarization assembly for use in electrochemical mechanical planarization is provided. A conductive planarization assembly in accordance with an exemplary embodiment of the invention comprises a first insulating member and a second insulating member overlying the first insulating member and having a plurality of first holes. A conductive member is interposed between the first insulating member and the second insulating member and is electrically coupled to an external circuit. The conductive member comprises a plurality of cathode regions that are exposed by the plurality of first holes of the second insulating member.

Abstract: Methods for depositing a tungsten nitride layer are described. The methods form a tungsten nitride layer using a carefully controlled deposition technique such as pulsed nucleation layer (PNL). Initially, a tungsten layer is formed on a substrate surface. The tungsten layer is then exposed to a nitriding agent to form a tungsten nitride layer. Methods of forming relatively thick layers of involve repeated cycles of contact with reducing agent, tungsten precursor and nitriding agent. In some cases, the cycle may also include contact with a dopant precursor such as phosphine or arsine.

Abstract: During fluid treatment of a substrate surface, a carrier/wafer assembly containing a substrate wafer closes the top of a microcell container. The carrier/wafer assembly and the container walls define a thin enclosed treatment volume that is filled with treating fluid, such as electroless plating solution. The thin fluid-treatment volume typically has a volume in a range of about from 100 ml to 500 ml. Preferably a container is heated and the treating fluid is pre-heated before being injected into the container. Preferably, the chemical composition, temperature, and other properties of fluid in the thin enclosed fluid-treatment volume are dynamically variable. A rinse shield and a rinse nozzle are located above the container. A carrier/wafer assembly in a rinse position substantially closes the top of the rinse shield.

Abstract: Pad-assisted electropolishing of the substrate is conducted by performing anodic dissolution of metal at a first portion of the substrate and simultaneously mechanically buffing a second portion of the substrate with a buffing pad. Anodic dissolution includes forming a thin liquid layer of electropolishing liquid between the anodic substrate and a cathodic electropolishing head. The location of electrical contacts between the substrate and power supply allow peripheral edge regions of the substrate to be mechanically buffed with the pad. Preferably, a substrate is further planararized using an isotropic material-removal technique. An apparatus includes an electropolishing head that is movable to a position proximate to a first portion of a substrate to form a thin gap, and a buffing pad that mechanically buffs a second portion of the substrate using minimal pressure.

Abstract: The orientation of a wafer with respect to the surface of an electrolyte is controlled during an electroplating process. The wafer is delivered to an electrolyte bath along a trajectory normal to the surface of the electrolyte. Along this trajectory, the wafer is angled before entry into the electrolyte for angled immersion. A wafer can be plated in an angled orientation or not, depending on what is optimal for a given situation. Also, in some designs, the wafer's orientation can be adjusted actively during immersion or during electroplating, providing flexibility in various electroplating scenarios.

Abstract: A work piece is electroplated or electroplanarized using an azimuthally asymmetric electrode. The azimuthally asymmetric electrode is rotated with respect to the work piece (i.e., either or both of the work piece and the electrode may be rotating). The azimuthal asymmetry provides a time-of-exposure correction to the current distribution reaching the work piece. In some embodiments, the total current is distributed among a plurality of electrodes in a reaction cell in order to tailor the current distribution in the electrolyte over time. Focusing elements may be used to create “virtual electrode” in proximity to the surface of the work piece to further control the current distribution in the electrolyte during plating or planarization.

Abstract: Metal seed layers are deposited on a semiconductor substrate having recessed features by a method that involves at least three operations. In this method, a first layer of metal is deposited onto the substrate to cover at least the bottom portions of the recessed features. The first layer of metal is subsequently redistributed to improve sidewall coverage of the recessed features. Next, a second layer of metal is deposited on at least the field region of the substrate and on the bottom portions of the recessed features. The method can be implemented using a PVD apparatus that allows deposition and resputtering operations. This sequence of operations can afford seed layers with improved step coverage. It also leads to decreased formation of voids in interconnects, and to improved resistance characteristics of formed IC devices.

Abstract: A deposition method modulates the reaction rate and thickness of highly conformal dielectric films deposited by forming a saturated catalytic layer on the surface and then exposing the surface to silicon-containing precursor gas and a reaction modulator, which may accelerate or quench the reaction. The modulator may be added before, after, or during exposure of the silicon-containing precursor gas. The film thickness after one cycle of deposition may be increased up to 20 times or decreased up to 20 times.

Abstract: The present invention relates to a cyclic deposition process suitable for depositing an elemental film. The process employs an enhanced atomic layer deposition technique.

Abstract: Methods of producing low resistivity tungsten bulk layers having lower roughness and higher reflectivity are provided. The smooth and highly reflective tungsten layers are easier to photopattern than conventional low resistivity tungsten films. The methods involve CVD deposition of tungsten in the presence of alternating nitrogen gas pulses, such that alternating portions of the film are deposited by CVD in the absence of nitrogen and in the presence of nitrogen. According to various embodiments, between 20-90% of the total film thickness is deposited by CVD in the presence of nitrogen.

Abstract: Methods for fabricating semiconductor structures with backside stress layers are provided. In one exemplary embodiment, the method comprises the steps of providing a semiconductor device formed on and within a front surface of a semiconductor substrate. The semiconductor device comprises a channel region. A plurality of dielectric layers is formed overlying the semiconductor device. The plurality of dielectric layers comprises conductive connections that are in electrical communication with the semiconductor device. A backside stress layer is formed on a back surface of the semiconductor substrate. The backside stress layer is configured to apply to the channel region of the semiconductor device a uniaxial compressive or tensile stress that, with stresses applied by the plurality of dielectric layers, results in an overall stress exerted on the channel region to achieve a predetermined overall strain of the channel region.

Abstract: An apparatus for electroplating a layer of metal onto the surface of a wafer includes an ionically resistive ionically permeable element located in close proximity of the wafer and an auxiliary cathode located between the anode and the ionically resistive ionically permeable element. The ionically resistive ionically permeable element serves to modulate ionic current at the wafer surface. The auxiliary cathode is configured to shape the current distribution from the anode. The provided configuration effectively redistributes ionic current in the plating system allowing plating of uniform metal layers and mitigating the terminal effect.

Abstract: A substantially uniform layer of a metal is electroplated onto a work piece having a seed layer thereon. This is accomplished by employing a “high resistance ionic current source,” which solves the terminal problem by placing a highly resistive membrane (e.g., a microporous ceramic or fretted glass element) in close proximity to the wafer, thereby swamping the system's resistance. The membrane thereby approximates a constant current source. By keeping the wafer close to the membrane surface, the ionic resistance from the top of the membrane to the surface is much less than the ionic path resistance to the wafer edge, substantially compensating for the sheet resistance in the thin metal film and directing additional current over the center and middle of the wafer.