Abstract: There is provided a computer-implemented method for verification of a layout of an integrated circuit according to a design intent with a selected manufacturing process. The method comprises defining corner points of a first circuit part 1 as seed points 3, projecting a specifically designed polygon shape 4 proximal to a seed point 3 and calculating an overlap area 5 between the projected polygon shape 4 and a second circuit part 2. The layout is rejected when the overlap area does not conform to a threshold overlap area determined by the design intent.

Abstract: There is provided a computer-implemented method for verification of a layout of an integrated circuit according to a design intent with a selected manufacturing process. The method comprises defining corner points of a first circuit part 1 as seed points 3, projecting a specifically designed polygon shape 4 proximal to a seed point 3 and calculating an overlap area 5 between the projected polygon shape 4 and a second circuit part 2. The layout is rejected when the overlap area does not conform to a threshold overlap area determined by the design intent.