Abstract: A pin electronics circuit for use in automatic test equipment may include a reconfigurable logic device in which different logic configurations may be installed to make measurements according to multiple tests to be applied to a device under test; a level generating circuit coupled to the reconfigurable logic device, and configured to generate a number of test levels and a number of reference levels; and a switching circuit, coupled to the reconfigurable logic device and the level generating circuit, configured to receive the test levels and the reference levels, and controlled by the reconfigurable logic device to selectively apply the test levels to the device under test according to a selected test and to sense levels inputted to or outputted from the device under test by comparing the reference levels generated by the level generating circuit to the levels inputted to our outputted from the device under test.

Abstract: Methods for integrated circuit diagnosis, characterization or modification using a charged particle beam. In one implementation, the bulk silicon substrate of an integrated circuit is thinned to about 1 to 3 ?m from the deepest well, a voltage is applied to a circuit element that is beneath the outer surface of the thinned substrate. The applied voltage induces an electrical potential on the outer surface, which is detected as a surface feature on the outer surface by its interaction with the charged particle beam.

Abstract: Methods and apparatus, including computer program products, implementing and using techniques for open-loop waveform acquisition. In general, in one aspect, the invention provides a method for open-loop waveform acquisition. The method includes acquiring an S-curve of an acquisition loop of an electron-beam probe system. The S-curve represents a response of the acquisition loop to changes of potential differences between the acquisition loop and a device under test. The method includes calibrating the acquisition loop to obtain a linear region in the acquired S-curve and using the linear portion of the acquired S-curve to calculate voltage at a probe point of the device under test.

Abstract: A comparator circuit includes at least one transconductance stage that receives two test voltages and two reference voltages. The transconductance stage produces two test currents that are proportional to the test voltages and two reference currents. A switching circuit is coupled to the transconductance stage. The switching circuit has two output terminals that are coupled to a conventional comparator stage. The switching circuit can combine the test currents with the reference currents to realize a differential swing comparison mode and a common-mode comparison mode as required for testing differential signals. Moreover, by disabling appropriate output signals from the at least one transconductance stage, a single-ended comparison mode is realized. By using two identical transconductance amplifiers, the non-linearity of the transconductance stage is advantageously canceled out.

Abstract: The present invention provides a method and system for testing a semiconductor device under test (DUT), such as an IC, with the help of a tester. A clock generator in the tester generates a clock signal that is sent over to the DUT on a clock signal line. Prior to an actual test, transmission and reception of data between the tester and the DUT, is synchronized with the clock signals. The invention utilizes simultaneous bi-directional signaling (SBS) for simultaneously transmitting and receiving test related data between the tester and the DUT over a single transmission line. The DUT replies with response signals corresponding to these test related data over the same transmission line. The use of SBS reduces the time required for the test, the number of pins and hence, overall cost and complexity of the testing process involved with the test.

Abstract: A method and apparatus for accessing internal nodes of an integrated circuit using a package substrate are provided. Embodiments of the present invention include an integrated circuit comprising an integrated circuit die comprising a principal side; a conductive element formed on the principal side of the integrated circuit die; a package substrate comprising a principal side facing the principal side of the integrated circuit die; a conductive element located on the principal side of the package substrate; a transmission path wherein a first end of the transmission path is coupled to the conductive element of the integrated circuit die and wherein a second end of the transmission path is coupled to the conductive element of the package substrate.

Abstract: A heat-sinking apparatus (62, 64, 66, and 68) containing a light-transparent pane (72) is configured in a way that enables the pane to be brought into contact with a device (40) such as a semiconductor device without significantly damaging the pane. A main spreader body (120) of a heat spreader (66) in the heat-sinking apparatus preferably consists largely of copper and is connected to the pane, preferably consisting largely of diamond, by way of a combination of metals that facilitates heat transfer from the pane to the heat spreader.

Abstract: A method for surface preparation of a polycrystalline material prior to etching. The material surface is effectively amorphized by two particle beam bombardments on the material surface. These energized particles break the crystal structure of the crystalline material and convert it effectively into an amorphous material. The two particle beams are oriented to each other at an angle of at least twice of the critical angle of channeling for the most open crystal structure in the material. This ensures effective amorphization of the material surface regardless of the different grain orientations on the surface. The amorphized surface has isotropic surface properties and thus allows uniform etching at the second angle. The uniformity in surface properties allows better control over etching process and reduces damage to underlying and adjacent material.

Abstract: A method for surface preparation of a polycrystalline material prior to etching. The material surface is amorphized by two particle beam bombardments s on the material surface. These energized particles break the crystal structure of the crystalline material and convert it into amorphous material. The two particle beams are oriented to each other at an angle of at least twice of the critical angle of channeling for the most open crystal structure in the material. This ensures amorphization of the material surface regardless of the different grain orientations on the surface. The amorphous surface has isotropic surface properties and thus allows uniform etching. The uniformity in surface properties allows better control over etching process and reduces damage to underlying and adjacent material.

Abstract: A test system includes (a) a tester mechanism (16 and 42) having tester contacts (152) for carrying test signals, (b) an interface module (44), and (c) a device-side board (46) having device-side contacts (162) for connection to external leads of an electronic device (40) under test. The interface module contains a tester-side body (50) having tester-side openings (86) for being positioned opposite the tester contacts, a device-side body (52) having device-side openings (136) for being positioned opposite the device-side contacts, and interface conductors (54) extending through the tester-side and device-side openings for connecting the tester contacts to the device-side contacts. The tester body is configured, typically as at least five wedge-shaped portions (68), in such a manner as to enable the electronic device under test to have an increased number of external leads.