Abstract: Apparatus and method for exposing a selected feature of an integrated circuit device such as a selected portion of the metallization layer, from the backside of the integrated circuit substrate without disturbing adjacent features of the device such as the active semiconductor regions. This is performed using an FIB (focused ion beam) etching process in conjunction with observation by an optical microscope to form a trench through the substrate. The floor of the trench is formed so as to be as smooth and planar as possible, thereby preventing undesirable exposure of the underlying active regions through any unknown or undesired cavity caused by scratches or pits or a deeper than desired sidewall.

Abstract: Method and apparatus for calibrating timing accuracy during testing of integrated circuits. An ATE type (automatic test equipment) integrated circuit tester calibrates itself to reference blocks (dummy ICs) that have the same relevant dimensions as the integrated circuits to be tested and have fit into the test fixture. The number of reference blocks required is equal to the number of signal terminals on the integrated circuit to be tested subject to timing calibration where typically the number of signal terminals is less than the total number of signal terminals on the IC being tested and is typically a relatively small number, e.g., 9. This is useful in the case of high pin count integrated circuits where the pins are grouped into relatively small numbers of pins which are source synchronous. A signal trace electrically connects a different signal terminal to a common reference terminal on each reference block in the set.

Abstract: A method and associated apparatus for testing devices outputting source synchronous signals using automated test equipment (“ATE”). An output data signal and an output clock signal from such a source synchronous device under test are delayed using a delay network. The delay provides the time required to deskew path errors and to buffer and distribute the output clock signal. The output data signal appears relatively stable to the ATE by reading the output data signal using the output clock signal.

Abstract: A system and method for processing scan data for integrated circuit testing. Scan data is divided into three groups of scan data segments: scan-in data segments, scan-out data segments and scan-mask data segments. The sequence of scan data segments in each group constitutes the operative test data in a scan stream. Each scan stream is represented by a table having a row corresponding to each scan data segment in the stream. Each row has four fields: a start address, a segment length, a start pad length and an end pad length. The start address is a pointer to the scan data segment in memory where the scan data segment is stored in a contiguous portion of memory. Scan data segment length is the length in bits of the segment. Start pad length is a delay value measured in number of scan clock cycles that must elapse before processing the respective segment in the scan stream.

Abstract: A test system for testing an electronic device is deployable in two basic configurations. In one of the configurations, a load board (62) that receives a unit (60) of the device is directly attached to a test head (16). In the other configuration, the same load board or one having largely the same pattern of test-head signal transmission positions is coupled through an interface apparatus (66) to a test head. A probe system (64) contacts that load board or/and the interface apparatus. The interface apparatus is normally configured to largely prevent test-head vibrations from being transferred to the probe system. Additionally or alternatively, the load board is vacuum attached to the interface apparatus.

Abstract: A method of probing voltage comprises: establishing electrical connectivity between a conductor to be probed and a first terminal of a photoconductive switch; during a sampling interval n, applying a laser pulse to the photoconductive switch while applying a voltage to a second terminal of the photoconductive switch corresponding to a voltage sample taken during a prior sampling interval n−1, such that current flow through the photoconductive switch is dependent on any difference between voltage of the conductor and the applied voltage; converting the current flow to a voltage signal; passing the voltage signal during a gating interval and sampling the passed voltage signal to produce a voltage sample for the sampling interval n. A repetitive test pattern applied to the conductor and the sampling interval is synchronized with the repetitive test pattern.

Abstract: A reliable, inexpensive “back side” thinning process, capable of globally thinning an integrated circuit die to a target thickness of 10 microns, and maintaining a yield of at least 80%, for chip repair and/or failure analysis of the packaged die. The flip-chip packaged die is exposed at its backside and mounted on a lapping machine with the backside exposed. The thickness of the die is measured at at least five locations on the die. The lapping machine grinds the exposed surface of the die to a thickness somewhat greater than the target thickness. The exposed surface of the die is polished. The thickness of the die is again measured optically with high accuracy. Based on the thickness data collected, appropriate machine operating parameters for further grinding and polishing of the exposed surface are determined. Further grinding and polishing are performed. These steps are repeated until the target thickness is reached.

Abstract: A scintillator assembly used in a FIB (Focused Ion Beam) system to detect secondary electrons achieves nearly 100 percent collection efficiency for the majority of useful secondary electron energy ranges. Further, the insulator in the assembly is placed such that it is completely out of the secondary electron path in order to avoid arcing which affects FIB secondary electron imaging. Also, the gap between the grounding cap and the scintillator allows high collection efficiency offered by earlier designs to be retained, and at the same time, improves the system reliability. Further, the scintillator assembly may be placed closer to the primary ion beam, which further improves collection efficiency.

Abstract: An apparatus compares propagation delay of electronic by using flip-flops or similar storage elements. The apparatus includes a strobe source having an output line coupled to a control terminal of a pattern source and an input terminal of a variable clock delay. The strobe source triggers the pattern source to output signal a sequence of signals to an input terminal of an element or device under test (DUT). The DUT propagates the signals to a flip-flop. The output signal of the flip-flop is captured after a delay. The propagation delay of the DUT is determined by coinciding the clock signal edge with the data signal edge to the flip-flop so that the flip-flop enters the ambiguity region. Once the delay settings that define the ambiguity region under the same delay are determined for various DUTs, they are compared to determine which DUT has the least propagation delay.